公开(公告)号：US20240249992A1

公开(公告)日：2024-07-25

申请号：US18099389

申请日：2023-01-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L23/34 ,  H01L29/737

CPC classification number: H01L23/345 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.

公开(公告)号：US12047068B2

公开(公告)日：2024-07-23

申请号：US18080378

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Shivraj G. Dharne

IPC: H03K19/01 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/00361

Abstract: The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.

公开(公告)号：US20240242013A1

公开(公告)日：2024-07-18

申请号：US18153799

申请日：2023-01-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Romain H.A. FEUILLETTE ,  Mujahid MUHAMMAD ,  Alain F. LOISEAU

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2111/02

Abstract: The present disclosure relates to relates to integrated circuits and, more particularly, to trusted Pcells leveraging smart contracts on a blockchain and methods of manufacture. In particular, the structure includes a first parameterized cell (Pcell) label generated based on a customer label corresponding to a customer design on a customer network and which comprises a real-time transaction validation for a smart contract on a blockchain network.

公开(公告)号：US20240241313A1

公开(公告)日：2024-07-18

申请号：US18619985

申请日：2024-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/126

CPC classification number: G02B6/1228 ,  G02B6/126

Abstract: Disclosed is a structure including a polarization device with first and second waveguides. The first waveguide includes a core (e.g., a silicon nitride (SiN) core) suitable for high-power applications. The second waveguide includes: a primary core (e.g., another SiN core), which is positioned laterally adjacent to the core of the first waveguide and suitable for high-power applications, and secondary core(s) stacked vertically with the primary core to steer the optical mode and ensure that mode matching occurs between adjacent first and second coupling sections of the first and second waveguides, respectively, in order to achieve high-power splitter and/or combiner functions. Optionally, the primary and secondary cores of the second waveguide can be tapered at least within the second coupling section to increase the likelihood of mode matching.

公开(公告)号：US12040252B2

公开(公告)日：2024-07-16

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L21/762 ,  H01L23/367 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L21/76229 ,  H01L23/367 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US12038615B2

公开(公告)日：2024-07-16

申请号：US17701918

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/42

CPC classification number: G02B6/4203 ,  G02B6/42

Abstract: Structures for an edge coupler and methods of fabricating such structures. The structure includes a substrate, a first waveguide core, and a second waveguide core positioned in a vertical direction between the first waveguide core and the substrate. The second waveguide core includes a taper and an inverse taper longitudinally positioned adjacent to the taper.

公开(公告)号：US20240234533A1

公开(公告)日：2024-07-11

申请号：US18152710

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：US20240224515A1

公开(公告)日：2024-07-04

申请号：US18149733

申请日：2023-01-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Violetta Sessi

IPC: H10B41/30

CPC classification number: H10B41/30

Abstract: The disclosure provides a structure with a buried doped region for coupling a source line contact to the gate structure of a memory cell. A structure according to the disclosure includes a memory cell having a gate structure extending in a first lateral direction over a substrate. A buried doped region is within the substrate and extends in a second lateral direction from below the gate structure to a portion of the substrate laterally distal to the gate structure. A source line contact is on the portion of the substrate laterally distal to the gate structure. The buried doped region couples the source line contact to the gate structure of the memory cell through a lower surface of the gate structure.

公开(公告)号：US20240222366A1

公开(公告)日：2024-07-04

申请号：US18604627

申请日：2024-03-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.