公开(公告)号：US20090001341A1

公开(公告)日：2009-01-01

申请号：US11771501

申请日：2007-06-29

申请人： Matthew Breitwisch ,  Thomas Happ ,  Eric A. Joseph ,  Hsiang-Lan Lung ,  Jan Boris Philipp

发明人： Matthew Breitwisch ,  Thomas Happ ,  Eric A. Joseph ,  Hsiang-Lan Lung ,  Jan Boris Philipp

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.

摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。 本发明的另一实施例包括可配置为用作非易失性存储元件的相变存储器（PCM）结构。 该元件包括至少一个底部电极; 在所述底部电极的上表面的至少一部分上的至少一个相变材料层; 以及在所述相变材料层的上表面的至少一部分上的至少一个加热层，其中所述加热器层具有锥形形状，使得所述加热器层的上表面的横截面宽度比 加热器层的底表面的与相变材料层接触的横截面宽度。

公开(公告)号：US20080274585A1

公开(公告)日：2008-11-06

申请号：US12174496

申请日：2008-07-16

申请人： Hsiang Lan LUNG ,  Shih Hung CHEN

发明人： Hsiang Lan LUNG ,  Shih Hung CHEN

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/79 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

摘要： A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.

摘要翻译： 一种存储装置，包括具有顶侧的侧壁的第一盘形电极，具有顶侧的侧壁和在第一侧壁和第二侧壁之间的绝缘壁的第二盘形电极。 绝缘壁在相应顶面附近的第一和第二侧壁之间具有厚度。 记忆材料桥跨越绝缘壁，并且在绝缘壁之间限定第一和第二电极之间的电极间路径。 提供这样的存储单元阵列。 记忆材料的桥梁具有亚光刻尺寸。

公开(公告)号：US20080224119A1

公开(公告)日：2008-09-18

申请号：US12130075

申请日：2008-05-30

申请人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

发明人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/122 ,  G11C13/0004 ,  G11C2213/55 ,  H01L45/06 ,  H01L45/1675

摘要： Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

摘要翻译： 具有通过重叠薄膜形成的具有小的相变开关体积的薄膜相变存储器。 示例性实施例包括相变存储元件，包括具有电阻的第一相变层，具有电阻的第二相变层，设置在第一和第二相变层之间的绝缘层; 以及具有电阻的第三相变层，并且耦合到所述第一和第二相变层中的每一个，桥接所述绝缘层并电耦合所述第一和第二相变层，其中所述第三相变层的电阻大于 第一相变层和第二相变层的电阻。

公开(公告)号：US20080197334A1

公开(公告)日：2008-08-21

申请号：US11677416

申请日：2007-02-21

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： H01L45/00

CPC分类号： H01L45/148 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

摘要： A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated top and bottom electrodes having mutually opposed contact surfaces. A sub-lithographic pillar of memory material, which in a particular embodiment is a chalcogenide, is encased within the dielectric material layer. A heater between the pillar of programmable resistive material and the top electrode forms an active region, or programmable resistive change region, next to the heater when the memory device is programmed or reset.

摘要翻译： 具有薄加热器的存储器件在可编程电阻变化材料（“存储材料”）的亚光刻柱中形成可编程电阻变化区域，其中加热器形成在顶部电极和可编程材料之间的柱内。 该器件包括介电材料层和具有相互相对的接触表面的垂直分离的顶部和底部电极。 在特定实施例中，存储材料的亚光刻柱是硫族化物，被封装在电介质材料层内。 当可编程电阻材料的支柱与顶部电极之间的加热器在存储器件被编程或复位时在加热器旁边形成有源区或可编程电阻变化区。

公开(公告)号：US20080197333A1

公开(公告)日：2008-08-21

申请号：US11677392

申请日：2007-02-21

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

摘要： A memory device has a first electrode, a second electrode, and memory material defining an inter-electrode current path between the first electrode and the second electrode. A gap is formed by shrinkage of the shrinkable material between the memory material and a shrinkable material next to the memory material.

摘要翻译： 存储器件具有第一电极，第二电极和限定第一电极和第二电极之间的电极间电流路径的存储材料。 存储材料与存储材料旁边的可收缩材料之间的可收缩材料的收缩形成间隙。

公开(公告)号：US20080191187A1

公开(公告)日：2008-08-14

申请号：US11764678

申请日：2007-06-18

申请人： HSIANG LAN LUNG ,  CHIEH-FANG CHEN ,  YI-CHOU CHEN ,  SHIH HUNG CHEN ,  CHUNG HON LAM ,  ERIC ANDREW JOSEPH ,  ALEJANDRO GABRIEL SCHROTT ,  MATTHEW J. BREITWISCH ,  GEOFFREY WILLIAM BURR ,  THOMAS D. HAPP ,  JAN BORIS PHILIPP

发明人： HSIANG LAN LUNG ,  CHIEH-FANG CHEN ,  YI-CHOU CHEN ,  SHIH HUNG CHEN ,  CHUNG HON LAM ,  ERIC ANDREW JOSEPH ,  ALEJANDRO GABRIEL SCHROTT ,  MATTHEW J. BREITWISCH ,  GEOFFREY WILLIAM BURR ,  THOMAS D. HAPP ,  JAN BORIS PHILIPP

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.

摘要翻译： 用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。 沉积一层电极材料，使其与导电触点阵列可靠地电接触。 蚀刻电极材料以在对应的导电触点上形成电极柱的图案。 接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。 接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。 描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

公开(公告)号：US20080185730A1

公开(公告)日：2008-08-07

申请号：US12023978

申请日：2008-01-31

申请人： Hsiang-Lan Lung

发明人： Hsiang-Lan Lung

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device described herein includes a bit line having a top surface and a plurality of vias. The device includes a plurality of first electrodes each having top surfaces coplanar with the top surface of the bit line, the first electrodes extending through corresponding vias in the bit line. An insulating member is within each via and has an annular shape with a thickness between the corresponding first electrode and a portion of the bit line acting as a second electrode. A layer of memory material extends across the insulating members to contact the top surfaces of the bit line and the first electrodes.

摘要翻译： 本文描述的存储器件包括具有顶表面和多个通孔的位线。 该器件包括多个第一电极，每个第一电极具有与位线的顶表面共面的顶表面，第一电极延伸穿过位线中相应的通孔。 绝缘构件在每个通孔内，并且具有环形形状，其厚度在相应的第一电极和作为第二电极的位线的一部分之间。 存储材料层延伸穿过绝缘构件以接触位线和第一电极的顶表面。

公开(公告)号：US20080179584A1

公开(公告)日：2008-07-31

申请号：US11864273

申请日：2007-09-28

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： H01L47/00

CPC分类号： H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625

摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode, a memory element and a side electrode. The bottom electrode contacts the memory element at a first contact surface on the bottom of the memory element. The side electrode contacts the memory element at a second contact surface on the side of the memory element, where the second contact surface on the side faces laterally relative to the first contact surface on the bottom.

摘要翻译： 描述存储单元以及制造方法。 如本文所述的存储单元包括底电极，存储元件和侧电极。 底部电极在存储元件底部的第一接触表面处接触存储元件。 侧电极在存储元件一侧的第二接触表面处接触存储元件，其中侧面上的第二接触表面相对于底部上的第一接触表面横向。

公开(公告)号：US20080165571A1

公开(公告)日：2008-07-10

申请号：US11621431

申请日：2007-01-09

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： G11C11/56

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

摘要： A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing a first process to program input data, including setting up bias voltages on bit lines and word lines on the memory cells, determining if the input data for each memory cell corresponds to a set state and then setting such cells to a set state. The method further comprises executing a second process to program input data, determining if the input data for each memory cell corresponds to a reset state and then resetting such cells to a reset state.

摘要翻译： 公开了用于编程多个可编程电阻存储器单元的方法，系统和计算机程序产品。 该方法包括执行编程输入数据的第一过程，包括在存储器单元上的位线和字线上设置偏置电压，确定每个存储器单元的输入数据是否对应于设置状态，然后将这样的单元设置为一组 州。 该方法还包括执行第二处理程序以输入数据，确定每个存储器单元的输入数据是否对应于复位状态，然后将这样的单元复位到复位状态。

公开(公告)号：US20080144353A1

公开(公告)日：2008-06-19

申请号：US11610293

申请日：2006-12-13

申请人： Hsiang Lan Lung

发明人： Hsiang Lan Lung

IPC分类号： G11C7/00 ,  G11C11/56

CPC分类号： G11C13/0007 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/31 ,  G11C2213/32

摘要： A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The method further comprises executing the following for each memory cell: programming the memory cell to a lower resistance (SET) state if the resistance is at a higher resistance state and the input data corresponds to a first (SET) state and programming the memory cell to a higher resistance (RESET) state if the resistance is at a lower resistance state and the input data corresponds to a second (RESET) state.

摘要翻译： 公开了用于编程多个可编程电阻存储器单元的方法，系统和计算机程序产品。 该方法包括对每个存储单元执行以下操作：读取存储单元的电阻并读取对应于存储单元的输入数据。 该方法还包括对每个存储器单元执行以下操作：如果电阻处于较高电阻状态并且输入数据对应于第一（SET）状态并且对存储器单元进行编程，则将存储器单元编程为较低电阻（SET）状态 如果电阻处于较低电阻状态并且输入数据对应于第二（RESET）状态，则更高电阻（RESET）状态。