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    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS
    62.
    发明申请
    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
    半导体器件的输入缓冲电路

    公开(公告)号：US20100039142A1

    公开(公告)日：2010-02-18

    申请号：US12540496

    申请日：2009-08-13

    申请人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    发明人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153

    摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

    摘要翻译： 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME
    69.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
    占空比校正电路和半导体集成电路设备，包括它们

    公开(公告)号：US20090231006A1

    公开(公告)日：2009-09-17

    申请号：US12331294

    申请日：2008-12-09

    申请人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    发明人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    IPC分类号： H03K5/04

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K2005/00058

    摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

    摘要翻译： 占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号 控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发， 延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

    DUTY RATIO CORRECTION CIRCUIT
    70.
    发明申请
    DUTY RATIO CORRECTION CIRCUIT 审中-公开
    占空比校正电路

    公开(公告)号：US20090146700A1

    公开(公告)日：2009-06-11

    申请号：US12178475

    申请日：2008-07-23

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07

    摘要： A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.

    摘要翻译： 一种占空比校正电路，包括：参考时钟产生模块，被配置为产生与外部时钟的上升沿和下降沿同步并具有主要校正的占空比的第一和第二参考时钟;以及占空比调整块，用于产生第一和第二内部 响应于第一和第二参考时钟的时钟，并且通过根据根据第一和第二参考时钟的第一和第二参考时钟之间的相位差产生的多个数字控制信号来调整第一和第二参考时钟的占空比， 第二个内部时钟。