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44 条记录 (耗时 0.045 秒)

    DUTY RATIO CORRECTION CIRCUIT
    1.
    发明申请
    DUTY RATIO CORRECTION CIRCUIT 审中-公开
    占空比校正电路

    公开(公告)号：US20090146700A1

    公开(公告)日：2009-06-11

    申请号：US12178475

    申请日：2008-07-23

    申请人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Yong Ju Kim ,  Kun Woo Park ,  Kyung Hoon Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07

    摘要： A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.

    摘要翻译： 一种占空比校正电路，包括：参考时钟产生模块，被配置为产生与外部时钟的上升沿和下降沿同步并具有主要校正的占空比的第一和第二参考时钟;以及占空比调整块，用于产生第一和第二内部 响应于第一和第二参考时钟的时钟，并且通过根据根据第一和第二参考时钟的第一和第二参考时钟之间的相位差产生的多个数字控制信号来调整第一和第二参考时钟的占空比， 第二个内部时钟。

    Latency control circuit and method of controlling latency
    2.
    发明授权
    Latency control circuit and method of controlling latency 有权
    延迟控制电路和控制延迟的方法

    公开(公告)号：US08909972B2

    公开(公告)日：2014-12-09

    申请号：US13219620

    申请日：2011-08-27

    申请人： Kyung Hoon Kim ,  Hong Bae Kim

    发明人： Kyung Hoon Kim ,  Hong Bae Kim

    IPC分类号： G06F1/00 ,  H03L7/06

    CPC分类号： H03L7/06 ,  G11C7/222 ,  G11C2207/2272 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/10

    摘要： A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal.

    摘要翻译： 延迟控制电路包括：延迟锁定环（DLL），被配置为通过根据双锁定点中的任一个延迟时钟信号延迟时钟信号来产生DLL时钟信号，并且根据锁定点生成环路变化信号 更改; 控制单元，被配置为响应于复位信号产生等待时间控制信号，通过将复位信号延迟第一延迟时间而产生的延迟信号和环路变化信号; 以及延迟信号生成单元，被配置为响应于等待时间控制信号来调整命令信号的等待时间并输出等待时间信号。

    Data output timing control circuit for semiconductor apparatus
    3.
    发明授权
    Data output timing control circuit for semiconductor apparatus 有权
    半导体装置的数据输出定时控制电路

    公开(公告)号：US08872557B2

    公开(公告)日：2014-10-28

    申请号：US13601661

    申请日：2012-08-31

    申请人： Kyung Hoon Kim

    发明人： Kyung Hoon Kim

    IPC分类号： G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/2254

    摘要： A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

    摘要翻译： 一种用于半导体装置的数据输出定时控制电路包括相位调整单元。 相位调整单元被配置为将延迟控制码的代码值的读取命令的相位与通过将外部时钟延迟大到预定延迟量而获得的多个延迟时钟分别延迟，延迟 移位读取命令与可变延迟量一样大，并将延迟结果作为输出使能标志信号输出。

    Power interface circuit of contact IC card reader
    4.
    发明授权
    Power interface circuit of contact IC card reader 有权
    接触式IC卡读卡器电源接口电路

    公开(公告)号：US08610468B2

    公开(公告)日：2013-12-17

    申请号：US13142079

    申请日：2009-12-11

    申请人： Hyun Soo Park ,  Byeong Cheon Jeong ,  Kyung Hoon Kim ,  Yeon Seok Song ,  Min Gyu Maing ,  Hong Chul Lee

    发明人： Hyun Soo Park ,  Byeong Cheon Jeong ,  Kyung Hoon Kim ,  Yeon Seok Song ,  Min Gyu Maing ,  Hong Chul Lee

    IPC分类号： H03B1/00 ,  H03K3/00

    CPC分类号： G06K7/0086

    摘要： A power interface circuit of a contact integrated circuit (IC) card reader is provided. The power interface circuit includes a power control unit configured to invert, amplify and output a power control signal supplied from the outside, a switching diode unit configured to control on and off operations of a ground terminal transistor in a complementary transistor unit in response to an output signal of the power control unit, the complementary transistor unit in which complementary transistors transfer a power supply terminal voltage to a power output unit or mute a card power supply terminal of the power output unit to a ground voltage level while operating inversely to each other in response to a control signal directly input from the power control unit and a control signal input through the switching diode unit, and the power output unit configured to output a voltage input through the complementary transistor unit to a card power supply terminal of an IC card or maintain the card power supply terminal at the ground voltage level in response to operation of the complementary transistor unit.

    摘要翻译： 提供了一种接触式集成电路（IC）读卡器的电源接口电路。 电源接口电路包括：功率控制单元，被配置为反相，放大和输出从外部提供的功率控制信号;开关二极管单元，被配置为响应于互补晶体管单元控制互补晶体管单元中的接地端子晶体管的导通和截止操作 功率控制单元的输出信号，互补晶体管单元，其中互补晶体管单元将电源端子电压传递到功率输出单元或将功率输出单元的卡电源端子静音到地电压电平，同时彼此反向工作 响应于从功率控制单元直接输入的控制信号和通过开关二极管单元输入的控制信号，以及功率输出单元，被配置为将通过互补晶体管单元输入的电压输出到IC卡的卡供电端子 或者将卡电源端子保持在接地电压水平，以响应补充的操作 内置晶体管单元。

    Synchronization circuit
    5.
    发明授权
    Synchronization circuit 有权
    同步电路

    公开(公告)号：US08405437B2

    公开(公告)日：2013-03-26

    申请号：US13190079

    申请日：2011-07-25

    申请人： Kyung Hoon Kim

    发明人： Kyung Hoon Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/087 ,  H03L7/0814 ,  H03L7/0816

    摘要： A synchronization circuit includes a delay line, and a first loop and a second loop configured to share the delay line, and the second loop is activated when a number of unit delay cells used in the delay line is equal to or less than a predetermined number according to an operation of the first loop.

    摘要翻译： 同步电路包括延迟线，以及被配置为共享延迟线的第一回路和第二回路，并且当延迟线中使用的单元延迟单元的数量等于或小于预定数量时，第二回路被激活 根据第一循环的操作。

    Semiconductor memory apparatus
    6.
    发明授权
    Semiconductor memory apparatus 失效
    半导体存储装置

    公开(公告)号：US07983095B2

    公开(公告)日：2011-07-19

    申请号：US12345835

    申请日：2008-12-30

    申请人： Kyung Hoon Kim ,  Sang Sic Yoon ,  Hong Bae Kim

    发明人： Kyung Hoon Kim ,  Sang Sic Yoon ,  Hong Bae Kim

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1039 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

    摘要： A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data.

    摘要翻译： 半导体存储装置包括：第一数据选择部，输入第一数据和第二数据，并响应于地址信号输出第一数据和第二数据之一作为第一选择数据;第二数据选择部，输入第二数据 和第一选择数据，并且根据输入和输出模式将第二数据和第一选择数据中的一个作为第二选择数据输出，以及数据输出部分，被配置为输入第一和第二选择数据并输出第一和第二 输出数据。

    WASHING MACHINE AND METHOD OF CONTROLLING A WASHING MACHINE
    7.
    发明申请
    WASHING MACHINE AND METHOD OF CONTROLLING A WASHING MACHINE 有权
    洗衣机和洗衣机的控制方法

    公开(公告)号：US20090300852A1

    公开(公告)日：2009-12-10

    申请号：US12470804

    申请日：2009-05-22

    申请人： Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

    发明人： Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

    IPC分类号： D06F33/00 ,  D06F39/00

    CPC分类号： D06F35/007 ,  D06F37/203

    摘要： The present invention relates to a washing machine and a method of controlling a washing machine. According to the washing machine and the method of controlling the washing machine in accordance with the present invention, the drum is operated at a first speed so that laundry tumbles within the drum. A laundry amount within the drum during the first speed operation is sensed. The drum is driven at a second speed so that part of the laundry tumbles within the drum and another part of the laundry adheres to the drum. Operation commands for driving the drum subsequent to the first speed operation are changed based on the sensed laundry amount. Accordingly, at the time of a dehydration cycle, stability of the washing machine and laundry balancing can be ensured.

    摘要翻译： 本发明涉及洗衣机和洗衣机的控制方法。 根据本发明的洗衣机和洗衣机的控制方法，以第一速度操作滚筒，使得衣物滚筒内滚动。 感测在第一速度操作期间滚筒内的衣物量。 鼓以第二速度被驱动，使得衣物的一部分在滚筒内滚动，另一部分衣物粘附到滚筒上。 基于感测到的衣物量改变用于在第一速度操作之后驱动滚筒的操作命令。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

    THIN FILM TRANSISTOR SUBSTRATE CAPABLE OF AVOIDING APERTURE REDUCTION
    9.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE CAPABLE OF AVOIDING APERTURE REDUCTION 有权
    薄膜晶体管基板可以避免减少孔径

    公开(公告)号：US20080111956A1

    公开(公告)日：2008-05-15

    申请号：US11940067

    申请日：2007-11-14

    申请人： Chul Ho KIM ,  Kook Chul Moon ,  Jae Hyun Kim ,  Ho Suk Maeng ,  Sang Hoon Lee ,  Kyung Hoon Kim ,  Keun Woo Park

    发明人： Chul Ho KIM ,  Kook Chul Moon ,  Jae Hyun Kim ,  Ho Suk Maeng ,  Sang Hoon Lee ,  Kyung Hoon Kim ,  Keun Woo Park

    IPC分类号： G02F1/1335 ,  H01L21/84

    CPC分类号： G02F1/134309 ,  G02F1/133555 ,  G02F1/136213 ,  G02F1/1393 ,  G02F2001/134345 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

    摘要： A thin film transistor (TFT) substrate that is capable of providing a wide viewing angle and high contrast ratio without a decrease is aperture ratio is presented. The TFT substrate may be, for example, used with a patterned vertical alignment (PVA) mode LCD. The TFT substrate includes gate lines and data lines extending in non-parallel directions and a pixel electrode formed in a pixel region. The pixel region has two transmission regions separated from each other by a reflection region, and at least one of the gate lines is formed in the reflection region. A storage capacitor may also be formed in the reflection region. This configuration avoids the use of a bridge region between the two transmission regions that is responsible for aperture ratio decrease in the conventional configuration.

    摘要翻译： 提出了能够提供宽视角和高对比度而不降低的薄膜晶体管（TFT）基板的开口率。 TFT基板例如可以与图案化的垂直取向（PVA）模式的LCD一起使用。 TFT基板包括在非平行方向上延伸的栅极线和数据线以及形成在像素区域中的像素电极。 像素区域具有通过反射区域彼此分离的两个透射区域，并且至少一个栅极线形成在反射区域中。 还可以在反射区域中形成存储电容器。 这种构造避免了在传统配置中负责孔径比减小的两个传输区域之间的桥接区域的使用。