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    SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR TEACHER-FREE SELF-FEATURE DISTILLATION TRAINING OF MACHINE LEARNING MODELS
    62.
    发明申请
    SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR TEACHER-FREE SELF-FEATURE DISTILLATION TRAINING OF MACHINE LEARNING MODELS 有权

    公开(公告)号：US20250068916A1

    公开(公告)日：2025-02-27

    申请号：US18725028

    申请日：2022-02-21

    Applicant: Intel Corporation

    Inventor： Yurong Chen ,  Anbang Yao ,  Yi Qian ,  Yu Zhang ,  Shandong Wang

    IPC: G06N3/088

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for teacher-free self-feature distillation training of machine-learning (ML) models. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to perform a first comparison of (i) a first group of a first set of feature channels (FCs) of an ML model and (ii) a second group of the first set, perform a second comparison of (iii) a first group of a second set of FCs of the ML model and one of (iv) a third group of the first set or a first group of a third set of FCs of the ML model, adjust parameter(s) of the ML model based on the first and/or second comparisons, and, in response to an error value satisfying a threshold, deploy the ML model to execute a workload based on the parameter(s).

    REGION-BASED DETERMINISTIC MEMORY SAFETY
    63.
    发明申请
    REGION-BASED DETERMINISTIC MEMORY SAFETY 有权

    公开(公告)号：US20250068776A1

    公开(公告)日：2025-02-27

    申请号：US18948099

    申请日：2024-11-14

    Applicant: Intel Corporation

    Inventor： Michael LeMay ,  David M. Durham

    IPC: G06F21/79 ,  G06F12/0871 ,  G06F12/0882 ,  G06F21/55 ,  G06F21/60

    Abstract: Methods and apparatus relating to techniques for region-based deterministic memory safety are described. In some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. The portion of the data is stored in a first region of the memory. The first region of the memory includes a plurality of identically sized allocation slots. Other embodiments are also disclosed and claimed.

    DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS
    65.
    发明申请
    DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS 有权

    公开(公告)号：US20250068473A1

    公开(公告)日：2025-02-27

    申请号：US18453867

    申请日：2023-08-22

    Applicant: Intel Corporation

    Inventor： Jorge Eduardo Parra Osorio ,  Jiasheng Chen ,  Supratim Pal ,  James Valerio

    IPC: G06F9/50 ,  G06F9/30

    Abstract: Described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second hardware thread of the plurality of hardware threads of the processing resource and first circuitry configured to facilitate access to memory on behalf of the plurality of hardware threads and store metadata for memory access requests from the plurality of hardware threads.

    Apparatuses, methods, and systems for instructions for usage restrictions cryptographically tied with data
    67.
    发明授权
    Apparatuses, methods, and systems for instructions for usage restrictions cryptographically tied with data 有权

    公开(公告)号：US12238217B2

    公开(公告)日：2025-02-25

    申请号：US18589125

    申请日：2024-02-27

    Applicant: Intel Corporation

    Inventor： Jason W. Brandt

    IPC: H04L9/08 ,  G06F9/30 ,  H04L9/32

    Abstract: Systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. In one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.

    Fin smoothing and integrated circuit structures resulting therefrom
    70.
    发明授权
    Fin smoothing and integrated circuit structures resulting therefrom 有权

    公开(公告)号：US12237420B2

    公开(公告)日：2025-02-25

    申请号：US18643632

    申请日：2024-04-23

    Applicant: Intel Corporation

    Inventor： Cory Bomberger ,  Anand S. Murthy ,  Tahir Ghani ,  Anupama Bowonder

    IPC: H01L21/00 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

    Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

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