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    SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME
    61.
    发明申请
    SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20110227231A1

    公开(公告)日：2011-09-22

    申请号：US13111100

    申请日：2011-05-19

    Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

    Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

    IPC: H01L23/48

    CPC classification number: H01L21/76816 ,  H01L21/31144

    Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

    Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

    Semiconductor device and methods of manufacturing the same
    62.
    发明授权
    Semiconductor device and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US07968447B2

    公开(公告)日：2011-06-28

    申请号：US12465013

    申请日：2009-05-13

    Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

    Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76816 ,  H01L21/31144

    Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

    Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

    SEMICONDUCTOR DEVICE INCLUDING RESISTOR AND METHOD OF FABRICATING THE SAME
    63.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING RESISTOR AND METHOD OF FABRICATING THE SAME 有权
    包括电阻器的半导体器件及其制造方法

    公开(公告)号：US20110062508A1

    公开(公告)日：2011-03-17

    申请号：US12882436

    申请日：2010-09-15

    Applicant: Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

    Inventor： Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

    IPC: H01L29/788

    CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

    Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

    Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

    Method of forming minute patterns in semiconductor device using double patterning
    64.
    发明授权
    Method of forming minute patterns in semiconductor device using double patterning 有权
    使用双重图案化在半导体器件中形成微小图案的方法

    公开(公告)号：US07816270B2

    公开(公告)日：2010-10-19

    申请号：US12453307

    申请日：2009-05-06

    Applicant: Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

    Inventor： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

    IPC: H01L21/311

    CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

    Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

    Abstract translation: 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

    Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices
    65.
    发明申请
    Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices 有权
    具有窄导电线图案的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号：US20100155959A1

    公开(公告)日：2010-06-24

    申请号：US12645820

    申请日：2009-12-23

    Applicant: Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

    Inventor： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

    Abstract translation: 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

    METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES
    66.
    发明申请
    METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES 有权
    在集成电路设备中形成精细图案的方法

    公开(公告)号：US20100096719A1

    公开(公告)日：2010-04-22

    申请号：US12418023

    申请日：2009-04-03

    Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

    Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

    IPC: H01L29/06 ,  H01L21/762 ,  H01L23/544

    CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.

    Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。 间隔件形成在第一和第二掩模结构的相对侧壁上。 使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间​​选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物 以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。 可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征 。

    Semiconductor memory devices including an air gap and methods of fabricating the same
    70.
    发明授权
    Semiconductor memory devices including an air gap and methods of fabricating the same 有权
    包括气隙的半导体存储器件及其制造方法

    公开(公告)号：US09166012B2

    公开(公告)日：2015-10-20

    申请号：US14096195

    申请日：2013-12-04

    Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC: H01L29/788 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115

    CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    Abstract translation: 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

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