公开(公告)号：US08793638B2

公开(公告)日：2014-07-29

申请号：US13559081

申请日：2012-07-26

Applicant: Keuing Hui ,  Yen-Wei Cheng ,  Yen-Di Tsen ,  Jong-I Mou ,  Chin-Hsiang Lin

Inventor： Keuing Hui ,  Yen-Wei Cheng ,  Yen-Di Tsen ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract translation: 本公开描述了优化用于制造（DFM）仿真的设计的方法。 该方法包括接收具有特征的集成电路（IC）设计数据，接收具有参数或多个参数的处理数据，执行DFM仿真和优化DFM仿真。 执行DFM模拟包括使用IC设计数据和过程数据生成模拟输出数据。 优化DFM模拟包括通过DFM仿真生成参数或多个参数的性能指标。 优化DFM模拟包括调整外循环，中间循环和内循环的参数或多个参数。 优化DFM模拟还包括在参数或多个参数的范围内定位参数或多个参数的性能指标的最低点。

公开(公告)号：US08606387B2

公开(公告)日：2013-12-10

申请号：US13006571

申请日：2011-01-14

Applicant: Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou

Inventor： Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou

IPC: G06F19/00

CPC classification number: G05B13/0265 ,  G05B19/41875 ,  G05B2219/32188 ,  G05B2219/32189 ,  G05B2219/45031 ,  Y02P90/22 ,  Y02P90/86

Abstract: A MIMO optimizer is used to identify tunable process parameters for processing equipment.

Abstract translation: MIMO优化器用于识别处理设备的可调工艺参数。

公开(公告)号：US08406904B2

公开(公告)日：2013-03-26

申请号：US13033413

申请日：2011-02-23

Applicant: Chih-Wei Hsu ,  Yen-Di Tsen ,  Jong-I Mou

Inventor： Chih-Wei Hsu ,  Yen-Di Tsen ,  Jong-I Mou

IPC: G05B13/02 ,  G06F19/00

CPC classification number: G05B19/41865 ,  G05B2219/32135 ,  G05B2219/32267 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/265

Abstract: The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

Abstract translation: 本公开提供了一种方法。 该方法包括从可用晶片的子集和可用处理室的子集中收集先进的过程控制（APC）数据。 该方法包括建立包含多个单元的矩阵。 每个单元对应于可用晶片之一和可用处理室之一。 通过填充已经收集了APC数据的单元格来部分填充矩阵。 该方法包括确定与矩阵相关联的多个腔室覆盖率（CCR）参数。 该方法包括通过迭代过程优化CCR参数以获得优化的CCR参数。 该方法包括基于优化的CCR参数预测矩阵的指定小区的APC数据值。 指定的单元格是在预测之前的空单元格，并由预测填充。

公开(公告)号：US08396583B2

公开(公告)日：2013-03-12

申请号：US12731407

申请日：2010-03-25

Applicant: Po-Feng Tsai ,  Andy Tsen ,  Jo Fei Wang ,  Jong-I Mou

Inventor： Po-Feng Tsai ,  Andy Tsen ,  Jo Fei Wang ,  Jong-I Mou

IPC: G06F19/00

CPC classification number: H01L22/20

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括分别从多个半导体处理中收集多个制造数据集。 该方法包括以制造数据组之间的统计差异减小的方式标准化每个制造数据组。 该方法包括建立包括标准化制造数据集的数据库。 该方法包括以使得归一化数据库中的制造数据集统统地与选定的一个制造数据集统计地兼容的方式对数据库进行归一化。 该方法包括通过使用归一化数据库来预测所选择的一个半导体处理的性能。 所选择的半导体工艺对应于所选择的制造数据集。 该方法包括响应于预测的性能来控制半导体处理机。

公开(公告)号：US08392009B2

公开(公告)日：2013-03-05

申请号：US12415366

申请日：2009-03-31

Applicant: Wang Jo Fei ,  Andy Tsen ,  Ming-Yu Fan ,  Jill Wang ,  Jong-I Mou

Inventor： Wang Jo Fei ,  Andy Tsen ,  Ming-Yu Fan ,  Jill Wang ,  Jong-I Mou

IPC: G06F19/00 ,  G01R31/26 ,  G06K9/00 ,  G06F17/50 ,  G01T1/24

CPC classification number: G05B21/02 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a first plurality of semiconductor wafers; determining a sampling rate to the first plurality of semiconductor wafers based on process quality; determining sampling fields and sampling points to the first plurality of semiconductor wafers; measuring a subset of the first plurality of semiconductor wafers according to the sampling rate, the sampling fields and the sampling points; modifying a second process according to the measuring; and applying the second process to a second plurality of semiconductor wafers.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括对第一多个半导体晶片执行第一处理; 基于过程质量确定对所述第一多个半导体晶片的采样率; 确定采样场和采样点到所述第一多个半导体晶片; 根据采样率，采样场和采样点测量第一多个半导体晶片的子集; 根据测量修改第二个过程; 以及将所述第二处理应用于第二多个半导体晶片。

公开(公告)号：US20120239178A1

公开(公告)日：2012-09-20

申请号：US13048282

申请日：2011-03-15

Applicant: Sunny Wu ,  Chun-Hsien Lin ,  Kun-Ming Chen ,  Dung-Yian Hsieh ,  Hui-Ru Lin ,  Jo Fei Wang ,  Jong-I Mou ,  I-Ching Chu

Inventor： Sunny Wu ,  Chun-Hsien Lin ,  Kun-Ming Chen ,  Dung-Yian Hsieh ,  Hui-Ru Lin ,  Jo Fei Wang ,  Jong-I Mou ,  I-Ching Chu

IPC: G06F19/00

CPC classification number: H01L22/20 ,  G01R31/2894 ,  H01L22/14

Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

Abstract translation: 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓，确定晶片产量测量对多个器件性能变量中的每一个的灵敏度，并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量，以提供组合晶片产量测量。 选择至少一个新的过程参数值，以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。

公开(公告)号：US20100248398A1

公开(公告)日：2010-09-30

申请号：US12412138

申请日：2009-03-26

Applicant: Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

Inventor： Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

IPC: H01L21/66 ,  B05C11/00 ,  H01L21/306

CPC classification number: H01L21/6831 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/909 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括对晶片执行第一处理; 在第一次处理之后测量晶片的晶片数据; 将晶片固定在处理室中的电子卡盘上; 从嵌入在E卡盘中的传感器收集传感器数据; 基于晶片数据和传感器数据调整到E型卡盘的夹紧力; 然后对固定在处理室中的E型卡盘上的晶片进行第二处理。

公开(公告)号：US20100210041A1

公开(公告)日：2010-08-19

申请号：US12370746

申请日：2009-02-13

Applicant: Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/26 ,  H01L21/265

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract translation: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源，每个冷却剂源流体耦合到相应的一个流体管道，并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。