公开(公告)号：US20100245138A1

公开(公告)日：2010-09-30

申请号：US12415012

申请日：2009-03-31

Applicant: Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

Inventor： Kameran Azadet ,  Samer Hijazi ,  Joseph H. Othmer

IPC: H03M1/06 ,  H03M3/00

CPC classification number: H03M7/3006 ,  H03M7/3042

Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.

Abstract translation: 提供了用于在Δ-Σ调制器中去量化量化噪声的方法和装置。 使用预测Δ-Σ调制器通过使用量化器量化输入信号来量化输入信号; 通过从量化器的输出中减去量化器的输入来确定与量化器相关联的量化误差; 测量量化误差与量化器的输入之间的相关系数; 通过从所述量化误差中减去所述量化器的输入的倍数来减少所测量的相关性，其中所述多个是基于所述相关系数; 使用误差预测滤波器生成误差预测值; 并从输入信号中减去误差预测值。

公开(公告)号：US20100198895A1

公开(公告)日：2010-08-05

申请号：US12362899

申请日：2009-01-30

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F7/00 ,  G06F15/00 ,  G06F7/52 ,  G06F7/50

CPC classification number: G06F7/556 ,  G06F1/0307 ,  G06F1/035 ,  G06F2101/10

Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value Log 2  ( 1 + 1 2  q ) from a first look-up table based on the second part, q; computing an epsilon term, ε, using the expression 2 - N 1 + 1 2  q  r ; evaluating an expression Log2 ( 1+ε) using a polynomial approximation, such as a cubic approximation; and determining the logarithm function for the input value, x, by summing the values of N, Log Z  ( 1 + 1 2  q ) and Log2(1+ε).

Abstract translation: 提供一种数字信号处理器，其具有使用缩减的查找表的具有对数函数的指令集。 所公开的数字信号处理器通过将输入值x分解为第一部分N，第二部分q和剩余部分r来评估输入值x的对数函数，其中第一部分N 由输入值x的最高有效位的位置识别，第二部分q由最高有效位之后的位数组成，其中该数目相对于位数 输入值x; 基于第二部分从第一查找表获得值Log 2（1 + 1 2 q）q， 使用表达式2-N 1 + 1 2 q计算ε项，egr; 使用多项式近似（例如立方近似）来评估表达式Log2（1 +＆egr;）; 并且通过将N，Log Z（1 + 1 2 q）和Log 2（1 +＆egr））的值求和来确定输入值x的对数函数。

公开(公告)号：US20100138465A1

公开(公告)日：2010-06-03

申请号：US12324934

申请日：2008-11-28

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F17/17

CPC classification number: G06F17/10 ,  G06F1/035 ,  G06F9/3001 ,  G06F9/383

Abstract: A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.

Abstract translation: 公开了使用因式分解多项式插值的一个或多个非线性函数的数字信号处理器和方法。 数字信号处理器通过从接近所述值x的所述非线性函数的至少一个查找表中获得两个或更多个值来评估值x的非线性函数; 并且使用因式分解多项式插值来内插所述两个或更多个获得的值以获得值y。

公开(公告)号：US07685640B2

公开(公告)日：2010-03-23

申请号：US10945663

申请日：2004-09-21

Applicant: Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

Inventor： Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

IPC: G06F7/04

CPC classification number: H04L63/145 ,  G06F21/564 ,  G06F21/566

Abstract: A virus detection mechanism is described in which virus detection is provided by a network integrated protection (NIP) adapter. The NIP adapter checks incoming media data prior to it being activated by a computing device. The NIP adapter operates independently of a host processor to receive information packets from a network. This attribute of independence allows NIP anti-virus (AV) techniques to be “always on” scanning incoming messages and data transfers. By being independent of but closely coupled to the host processor, complex detection techniques, such as using check summing or pattern matching, can be efficiently implemented on the NIP adapter without involving central processor resources and time consuming mass storage accesses. The NIP adapter may be further enhanced with a unique fading memory (FM) facility to allow for a flexible and economical implementation of polymorphic virus detection.

Abstract translation: 描述了病毒检测机制，其中病毒检测由网络集成保护（NIP）适配器提供。 NIP适配器在计算设备激活之前检查传入的媒体数据。 NIP适配器独立于主机处理器操作以从网络接收信息分组。 这种独立性允许NIP防病毒（AV）技术“永远在”扫描传入的消息和数据传输。 通过独立于主机处理器紧密耦合，可以在NIP适配器上有效地实现诸如使用校验和或模式匹配的复杂检测技术，而不涉及中央处理器资源和耗时的大容量存储访问。 NIP适配器可以通过独特的衰落存储器（FM）设施进一步增强，以允许灵活和经济地实施多态性病毒检测。

公开(公告)号：US20100034333A1

公开(公告)日：2010-02-11

申请号：US12187701

申请日：2008-08-07

Applicant: Kameran Azadet ,  Fuji Yang

Inventor： Kameran Azadet ,  Fuji Yang

IPC: H03D3/24

CPC classification number: H03B27/00

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract translation: 提供了用于在多相时钟/定时恢复系统中改善相位线性度的方法和装置。 平均和内插技术提高了多相时钟系统的相位线性度。 根据本发明的一个方面，通过产生多个具有基本相似的频率和不同相位的时钟来产生多相输出时钟; 将多个时钟中的每一个施加到至少一个对应的放大器，例如差分对电路; 并对相应放大器的输出求和以产生多相输出时钟。 多级平均操作可以进一步提高线性度。

公开(公告)号：US07610495B2

公开(公告)日：2009-10-27

申请号：US10874834

申请日：2004-06-23

Applicant: Kameran Azadet ,  Leilei Song

Inventor： Kameran Azadet ,  Leilei Song

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: H04W52/0277 ,  Y02D70/142

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract translation: 公开了一种用于电子设备的电源管理的方法和装置。 本发明通过在电池电平降低时通过选择具有降低的功耗的传输模式来降低通过网络进行通信的电子设备的功耗。 公开的电源管理过程监视电子设备的电池电量，并且当电池功率电平达到一个或多个预定阈值电平时，选择具有较低功耗的传输模式（例如，传输速率）。

公开(公告)号：US07577225B2

公开(公告)日：2009-08-18

申请号：US11191895

申请日：2005-07-28

Applicant: Kameran Azadet ,  Fuji Yang

Inventor： Kameran Azadet ,  Fuji Yang

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/093 ,  H03L7/0995 ,  H03L2207/50

Abstract: Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

Abstract translation: 本发明的实施例包括包括锁相环（PLL）的集成电路。 集成电路包括相位检测器，频率检测器，环路滤波器，数字控制振荡器和相应的多个分频器。 相位检测器基于参考时钟信号与多个时钟相位输入的相位比较来产生第一二进制输出。 频率检测器基于参考时钟信号与时钟相位输入的频率比较产生第二二进制输出。 环路滤波器基于第一个二进制输出和第二个二进制输出产生第三个二进制输出。 基于第三个二进制输出，DCO通过分频器将时钟相位输入反馈到相位检测器，并且基于第三个二进制输出将一个时钟相位反馈到频率检测器。

公开(公告)号：US07362719B2

公开(公告)日：2008-04-22

申请号：US10219906

申请日：2002-08-15

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H04B3/20

CPC classification number: H04J1/12 ,  H04J14/0298 ,  H04L5/06

Abstract: A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to baseband in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent RF channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit.

Abstract translation: 公开了用于在频分复用通信系统中消除串扰的方法和装置。 所公开的频分复用通信系统采用具有重叠信道的多个载波，并且提供改进的串扰消除机制来解决所产生的干扰。 在每个频带中使用n级幅度调制实现带宽压缩。 还公开了一种FDM接收机，其将接收的宽带信号分解成其各自的频带，并将该信号返回到模拟域中的基带。 通过从图像频带中消除相邻RF信道的串扰，并将调制器和解调器中的同相和正交相（I / Q）相位和增益失配引起的性能下降最小化，从而放宽模拟要求。 公开的发射器或接收器（或两者）可以在单个集成电路上制造。

公开(公告)号：US07355451B2

公开(公告)日：2008-04-08

申请号：US11141337

申请日：2005-05-31

Applicant: Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

Inventor： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

IPC: H03K19/0175

CPC classification number: H04L25/0282 ,  H03K19/09432 ,  H04L25/0274

Abstract: A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

Abstract translation: 公开了一种用于将CML器件的共模输出电压转换为任意电压的共模移位电路。 在CML设备的每个输出端提供恒流源。 恒定电流可以是正或负电流，分别提高或降低共模输出电压。 恒流源优选地连接到具有比CML器件的电源高的电压的交流电压源。 本发明还提供一种用于调整具有两个或多个输出端口的电流模式逻辑电路的输出信号的方法，包括在电流模式逻辑电路的每个输出端口处提供恒定电流的步骤，由此共模 所述电流模式逻辑电路的输出端口处的电压被电平移位。

公开(公告)号：US20060020877A1

公开(公告)日：2006-01-26

申请号：US11234446

申请日：2005-09-26

Applicant: Kameran Azadet ,  Erich Haratsch

Inventor： Kameran Azadet ,  Erich Haratsch

IPC: H03M13/03

CPC classification number: H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract translation: 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行）的增加的吞吐量相对于先行深度仅具有线性增加的硬件复杂度。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。