公开(公告)号：US20110242922A1

公开(公告)日：2011-10-06

申请号：US13158778

申请日：2011-06-13

申请人： Kyung Hoon KIM ,  Sang Sic YOON ,  Hong Bae KIM

发明人： Kyung Hoon KIM ,  Sang Sic YOON ,  Hong Bae KIM

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

摘要： A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data.

摘要翻译： 半导体存储装置包括：第一数据选择部，输入第一数据和第二数据，并响应于地址信号输出第一数据和第二数据之一作为第一选择数据;第二数据选择部，输入第二数据 和第一选择数据，并且根据输入和输出模式将第二数据和第一选择数据中的一个作为第二选择数据输出，以及数据输出部分，被配置为输入第一和第二选择数据并输出第一和第二 输出数据。

公开(公告)号：US08000166B2

公开(公告)日：2011-08-16

申请号：US12277609

申请日：2008-11-25

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

IPC分类号： G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

摘要翻译： 一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。 该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元 响应于第一和第二时钟传输线的输出时钟。

公开(公告)号：US07995171B2

公开(公告)日：2011-08-09

申请号：US11940067

申请日：2007-11-14

申请人： Chul Ho Kim ,  Kook Chul Moon ,  Jae Hyun Kim ,  Ho Suk Maeng ,  Sang Hoon Lee ,  Kyung Hoon Kim ,  Keun Woo Park

发明人： Chul Ho Kim ,  Kook Chul Moon ,  Jae Hyun Kim ,  Ho Suk Maeng ,  Sang Hoon Lee ,  Kyung Hoon Kim ,  Keun Woo Park

IPC分类号： G02F1/1335 ,  G02F1/136

CPC分类号： G02F1/134309 ,  G02F1/133555 ,  G02F1/136213 ,  G02F1/1393 ,  G02F2001/134345 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255

摘要： A thin film transistor (TFT) substrate that is capable of providing a wide viewing angle and high contrast ratio without a decrease is aperture ratio is presented. The TFT substrate may be, for example, used with a patterned vertical alignment (PVA) mode LCD. The TFT substrate includes gate lines and data lines extending in non-parallel directions and a pixel electrode formed in a pixel region. The pixel region has two transmission regions separated from each other by a reflection region, and at least one of the gate lines is formed in the reflection region. A storage capacitor may also be formed in the reflection region. This configuration avoids the use of a bridge region between the two transmission regions that is responsible for aperture ratio decrease in the conventional configuration.

摘要翻译： 提出了能够提供宽视角和高对比度而不降低的薄膜晶体管（TFT）基板的开口率。 TFT基板例如可以与图案化的垂直取向（PVA）模式的LCD一起使用。 TFT基板包括在非平行方向上延伸的栅极线和数据线以及形成在像素区域中的像素电极。 像素区域具有通过反射区域彼此分离的两个透射区域，并且至少一个栅极线形成在反射区域中。 还可以在反射区域中形成存储电容器。 这种构造避免了在传统配置中负责孔径比减小的两个传输区域之间的桥接区域的使用。

公开(公告)号：US07952438B2

公开(公告)日：2011-05-31

申请号：US12217049

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03B27/01

CPC分类号： H03L7/0812 ,  H03L7/18 ,  H03L7/24

摘要： An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

摘要翻译： 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。

公开(公告)号：US07948814B2

公开(公告)日：2011-05-24

申请号：US12164797

申请日：2008-06-30

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

摘要翻译： 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

公开(公告)号：US07894231B2

公开(公告)日：2011-02-22

申请号：US12483328

申请日：2009-06-12

申请人： Kyung Hoon Kim ,  Sang Sic Yoon

发明人： Kyung Hoon Kim ,  Sang Sic Yoon

IPC分类号： G11C5/02

CPC分类号： G11C8/06 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045

摘要： A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower order data of a plurality of data via lower data output pins. Also, when the first and second memory chips are in the first data output mode, the second memory chip is configured to externally output data that has the same order as the lower order data output by the first memory chip via upper data output pins.

摘要翻译： 存储器模块被配置为包括安装有第一存储器芯片的第一等级和安装有第二存储器芯片的第二等级。 当第一和第二存储器芯片处于第一数据输出模式时，第一存储器芯片被配置为经由下部数据输出引脚从外部输出多个数据的低阶数据。 此外，当第一和第二存储器芯片处于第一数据输出模式时，第二存储器芯片被配置为从外部输出与第一存储器芯片经由上部数据输出引脚输出的与低级数据相同的顺序的数据。

公开(公告)号：US07881139B2

公开(公告)日：2011-02-01

申请号：US12463838

申请日：2009-05-11

申请人： Kyung-Hoon Kim ,  Patrick B. Moran

发明人： Kyung-Hoon Kim ,  Patrick B. Moran

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G01K13/00 ,  G11C5/143 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4061

摘要： A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

摘要翻译： 半导体存储器件包括感测器件的当前温度并确认温度值是否有效的热敏传感器。 热敏传感器包括温度检测单元，存储单元和初始化单元。 温度感测单元响应于驱动信号感测温度。 存储单元存储温度感测单元的输出信号并输出​​温度值。 初始化单元在从驱动信号的激活开始的预定时间之后初始化存储单元。 驱动方法包括响应于驱动信号驱动热敏传感器，在从驱动信号的激活开始的预定时间之后请求重新驱动，并且响应于再次输入驱动信号重新驱动热敏传感器。

公开(公告)号：US07864624B2

公开(公告)日：2011-01-04

申请号：US12154936

申请日：2008-05-28

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC分类号： G11C8/18

CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result.

摘要翻译： 半导体存储器件包括：第一缓冲单元，被配置为缓冲用于地址信号的第一时钟和与第一时钟同步地输入的命令;第二缓冲单元，被配置为缓冲第二时钟以使数据信号同步 第二时钟输出具有与第一时钟相同频率的缓冲的第二时钟，数据输出电路被配置为响应于所缓冲的第二时钟输出内部数据;延迟单元，被配置为将缓冲的第二时钟延迟预定的 时间，以及相位检测器，被配置为检测延迟单元的输出时钟和第一缓冲单元的输出时钟的相位差，并输出检测结果。

公开(公告)号：US07863955B2

公开(公告)日：2011-01-04

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

公开(公告)号：US20100253610A1

公开(公告)日：2010-10-07

申请号：US12703730

申请日：2010-02-10

申请人： Seung-Kyu LEE ,  Chul-Ho Kim ,  Kyung-Min Park ,  Kyung-Hoon Kim ,  Jin-Suk Park

发明人： Seung-Kyu LEE ,  Chul-Ho Kim ,  Kyung-Min Park ,  Kyung-Hoon Kim ,  Jin-Suk Park

IPC分类号： G09G3/36 ,  H01L33/00

CPC分类号： G09G3/3611 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2320/0223

摘要： A display apparatus comprises a first thin film transistor (TFT) and a second TFT which are disposed in a display area. A first signal transmission line is disposed in a peripheral area surrounding the display area and is electrically connected to the first TFT. A second signal transmission line adjacent to the first signal transmission line is electrically connected to the second TFT. In a first portion of the peripheral area, the first signal transmission line is parallel to the second signal transmission line and is spaced by a first gap from the second signal transmission line. In a second portion of the peripheral area, the first signal transmission line is parallel to the second signal transmission line and is spaced by a second gap from and the second signal transmission line. The second gap is greater than the first gap. Other features are also provided.

摘要翻译： 显示装置包括设置在显示区域中的第一薄膜晶体管（TFT）和第二TFT。 第一信号传输线设置在围绕显示区域的周边区域中，并且电连接到第一TFT。 与第一信号传输线相邻的第二信号传输线电连接到第二TFT。 在外围区域的第一部分中，第一信号传输线路与第二信号传输线路平行，并与第二信号传输线路隔开第一间隙。 在外围区域的第二部分中，第一信号传输线平行于第二信号传输线，并与第二信号传输线隔开第二间隙。 第二个差距大于第一个差距。 还提供其他功能。