公开(公告)号：US20130271208A1

公开(公告)日：2013-10-17

申请号：US13977195

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract translation: 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。

公开(公告)号：US08384128B2

公开(公告)日：2013-02-26

申请号：US12454354

申请日：2009-05-15

Applicant: Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66477

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract translation: 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。

公开(公告)号：US08344425B2

公开(公告)日：2013-01-01

申请号：US12655463

申请日：2009-12-30

Applicant: Marko Radosavljevic ,  Uday Shah ,  Gilbert Dewey ,  Niloy Mukherjee ,  Robert S. Chau ,  Jack Kavalieros ,  Ravi Pillarisetty ,  Titash Rakshit ,  Matthew V. Metz

Inventor： Marko Radosavljevic ,  Uday Shah ,  Gilbert Dewey ,  Niloy Mukherjee ,  Robert S. Chau ,  Jack Kavalieros ,  Ravi Pillarisetty ,  Titash Rakshit ,  Matthew V. Metz

IPC: H01L29/12 ,  H01L21/20 ,  H01L21/336 ,  H01L21/18

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/785

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。

公开(公告)号：US08269209B2

公开(公告)日：2012-09-18

申请号：US12653847

申请日：2009-12-18

Applicant: Uday Shah ,  Benjamin Chu-Kung ,  Been Y. Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

Inventor： Uday Shah ,  Benjamin Chu-Kung ,  Been Y. Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

IPC: H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L2221/1094

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Abstract translation: 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。

公开(公告)号：US08258498B2

公开(公告)日：2012-09-04

申请号：US13017862

申请日：2011-01-31

Applicant: Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L31/0328 ,  H01L31/109

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US20120193609A1

公开(公告)日：2012-08-02

申请号：US13442098

申请日：2012-04-09

Applicant: Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20120168877A1

公开(公告)日：2012-07-05

申请号：US12982083

申请日：2010-12-30

Applicant: Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Robert S. Chau ,  Matthew V. Metz

Inventor： Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Robert S. Chau ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L21/205 ,  H01L21/203

CPC classification number: H01L21/28575 ,  H01L29/66446

Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

Abstract translation: 通常使用通过在源极和漏极中使用III-V半导体夹层来降低n沟道晶体管的接触电阻的方法。 在这方面，引入一种器件，其包括具有源极区和漏极区的n型晶体管，与晶体管相邻的第一层间电介质层，穿过第一层间介质层到源极区的沟槽，以及导电源接触 沟槽，源极触点通过III-V半导体夹层与源极区分离。 还公开并要求保护其他实施例。

公开(公告)号：US08193523B2

公开(公告)日：2012-06-05

申请号：US12655468

申请日：2009-12-30

Applicant: Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/08 ,  H01L29/12

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅介电材料允许使用高k值栅极电介质。

公开(公告)号：US20110312140A1

公开(公告)日：2011-12-22

申请号：US13216569

申请日：2011-08-24

Applicant: Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

Inventor： Ravi Pillarisetty ,  Jack Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/7391

Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

Abstract translation: 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。

公开(公告)号：US20110147798A1

公开(公告)日：2011-06-23

申请号：US12646711

申请日：2009-12-23

Applicant: Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。