公开(公告)号：US20140037991A1

公开(公告)日：2014-02-06

申请号：US13562873

申请日：2012-07-31

申请人： David W. Abraham ,  Michael C. Gaidis

发明人： David W. Abraham ,  Michael C. Gaidis

IPC分类号： G11B5/66

CPC分类号： G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49021 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A synthetic antiferromagnetic device includes a first tantalum layer, a reference layer disposed on the first tantalum layer and including a first cobalt iron boron layer, a second cobalt iron boron layer disposed on the first cobalt iron boron layer, a third cobalt iron boron layer and a second tantalum layer disposed between the second and third cobalt iron boron layers, a magnesium oxide spacer layer disposed on the reference layer and a cap layer disposed on the magnesium oxide spacer layer.

摘要翻译： 合成反铁磁装置包括第一钽层，设置在第一钽层上的参考层，并且包括第一钴铁硼层，设置在第一钴铁硼层上的第二钴铁硼层，第三钴铁硼层和 设置在第二和第三钴铁硼层之间的第二钽层，设置在参考层上的氧化镁间隔层和设置在氧化镁隔离层上的盖层。

公开(公告)号：US20140037990A1

公开(公告)日：2014-02-06

申请号：US13562868

申请日：2012-07-31

申请人： David W. Abraham ,  Michael C. Gaidis ,  Janusz J. Nowak ,  Daniel C. Worledge

发明人： David W. Abraham ,  Michael C. Gaidis ,  Janusz J. Nowak ,  Daniel C. Worledge

IPC分类号： G11B5/66

CPC分类号： G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  Y10T428/31953 ,  Y10T428/32 ,  Y10T428/325

摘要： A synthetic antiferromagnetic device includes a reference layer having a first and second ruthenium layer, a magnesium oxide spacer layer disposed on the reference layer, a cobalt iron boron layer disposed on the magnesium oxide spacer layer and a third ruthenium layer disposed on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0 angstroms to 18 angstroms.

摘要翻译： 合成反铁磁装置包括具有第一和第二钌层的参考层，设置在参考层上的氧化镁间隔层，设置在氧化镁间隔层上的钴铁硼层和设置在钴铁硼上的第三钌层 第三钌层的厚度为约0埃至18埃。

公开(公告)号：US08324734B2

公开(公告)日：2012-12-04

申请号：US13364494

申请日：2012-02-02

申请人： Michael C. Gaidis

发明人： Michael C. Gaidis

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5252 ,  H01L21/76886 ,  H01L27/18 ,  H01L27/222 ,  H01L39/2493 ,  H01L43/12 ,  H01L2924/0002 ,  Y10S438/979 ,  H01L2924/00

摘要： A memory device comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer; a top wiring layer; a plurality of TJs contacting the bottom wiring layer and the top wiring layer; and a plurality of tunnel junction vias (TJVs) contacting the bottom wiring layer and the top wiring layer, wherein the plurality of TJVs each have a lower resistance the each of the plurality of TJs, wherein the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs.

摘要翻译： 包括多个隧道结（TJ）的存储器件包括底部布线层; 顶部布线层; 与底部布线层和顶部布线层接触的多个TJ; 以及与所述底部布线层和所述顶部布线层接触的多个隧道结通孔（TJV），其中所述多个TJV各自具有每个所述多个TJ的较低电阻，其中所述多个TJV包括至少一个凹面 并且其中所述多个TJV的所述至少一个凹表面被配置为在形成所述TJV期间捕获蚀刻的材料，以便降低所述多个TJV的电阻。

公开(公告)号：US20120141748A1

公开(公告)日：2012-06-07

申请号：US13396998

申请日：2012-02-15

申请人： Michael C. Gaidis

发明人： Michael C. Gaidis

IPC分类号： B32B3/00

CPC分类号： H01L27/222 ,  B82Y10/00 ,  H01L43/12 ,  Y10S438/947 ,  Y10S977/888

摘要： A device comprising a diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and the diblock copolymer mask, the diblock copolymer mask comprising a first plurality of uniform shapes formed on and registered to the template.

摘要翻译： 包括用于制造磁阻随机存取存储器（MRAM）的二嵌段共聚物掩模的器件包括磁性层; 形成在磁性层上的掩模; 掩模上形成的模板; 和二嵌段共聚物掩模，二嵌段共聚物掩模包含形成在模板上并登记到模板上的第一多个均匀形状。

公开(公告)号：US08009453B2

公开(公告)日：2011-08-30

申请号：US12136089

申请日：2008-06-10

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： G11C19/08 ,  G11C19/38

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。

公开(公告)号：US20110204459A1

公开(公告)日：2011-08-25

申请号：US13100123

申请日：2011-05-03

申请人： Michael C. GAIDIS

发明人： Michael C. GAIDIS

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/08

摘要： A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls.

摘要翻译： 磁性隧道结装置包括包括图案化的布线层的基板。 在布线层上形成磁隧道结（MTJ）堆叠。 在MTJ堆叠上形成低导电层，并在其上形成导电硬掩模。 然后沉积包括与低电导率层不同的导电性的间隔物材料。 间隔材料从水平表面被蚀刻，使得间隔物材料仅保留在硬掩模和螺柱的侧壁上。 另外的蚀刻工艺在侧壁间隔材料之后留下了作为导电连接在自由磁性层和导电硬掩模之间的低电导率层周围。 螺柱和间隔物材料之间的导电性差异增强了沿着MTJ堆叠内的自由层的边缘的流动以及通过形成在侧壁上的间隔物材料的电流。

公开(公告)号：US20110163455A1

公开(公告)日：2011-07-07

申请号：US12683080

申请日：2010-01-06

申请人： Michael C. Gaidis

发明人： Michael C. Gaidis

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/5252 ,  H01L21/76886 ,  H01L27/18 ,  H01L27/222 ,  H01L39/2493 ,  H01L43/12 ,  H01L2924/0002 ,  Y10S438/979 ,  H01L2924/00

摘要： A method for forming a tunnel junction (TJ) circuit, the method includes forming a bottom wiring layer; forming a plurality of TJs contacting the bottom wiring layer; forming a plurality of tunnel junction vias (TJVs) simultaneously with the formation of the plurality of TJs, the TJVs contacting the bottom wiring layer; and forming a top wiring layer contacting the plurality of TJs and the plurality of TJVs. A circuit comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer contacting the plurality of TJs, the bottom wiring layer further contacting a plurality of tunnel junction vias (TJVs), wherein the plurality of TJs and the plurality of TJVs comprise the same material; and a top wiring layer contacting the plurality of TJs and the plurality of TJVs.

摘要翻译： 一种形成隧道结（TJ）电路的方法，所述方法包括形成底部布线层; 形成与底部布线层接触的多个TJ; 与形成多个TJ同时形成多个隧道结通孔（TJV），TJV接触底部布线层; 以及形成与所述多个TJ和所述多个TJV接触的顶部布线层。 包括多个隧道结（TJ）的电路包括与多个TJ接触的底部布线层，底部布线层还与多个隧道结通孔（TJV）接触，其中多个TJ和多个TJV包括 相同材料; 以及与多个TJ和多个TJV接触的顶部布线层。

公开(公告)号：US20100276768A1

公开(公告)日：2010-11-04

申请号：US12433023

申请日：2009-04-30

申请人： MICHAEL C. GAIDIS

发明人： MICHAEL C. GAIDIS

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/08

摘要： A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls.

摘要翻译： 磁性隧道结装置包括包括图案化的布线层的基板。 在布线层上形成磁隧道结（MTJ）堆叠。 在MTJ堆叠上形成低导电层，并在其上形成导电硬掩模。 然后沉积包括与低电导率层不同的导电性的间隔物材料。 间隔材料从水平表面被蚀刻，使得间隔物材料仅保留在硬掩模和螺柱的侧壁上。 另外的蚀刻工艺在侧壁间隔材料之后留下了作为导电连接在自由磁性层和导电硬掩模之间的低电导率层周围。 螺柱和间隔物材料之间的导电性差异增强了沿着MTJ堆叠内的自由层的边缘并且通过形成在侧壁上的间隔材料的电流流动。

公开(公告)号：US20090302405A1

公开(公告)日：2009-12-10

申请号：US12539942

申请日：2009-08-12

申请人： Michael C. Gaidis ,  Carl Radens ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Carl Radens ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： B82Y10/00 ,  H01L27/222 ,  H01L43/12

摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

摘要翻译： 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

公开(公告)号：US07544578B2

公开(公告)日：2009-06-09

申请号：US11619196

申请日：2007-01-03

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Michael C. Gaidis ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/20

CPC分类号： H01L23/576 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/20 ,  H01L28/40 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。