公开(公告)号：US08338815B2

公开(公告)日：2012-12-25

申请号：US12851268

申请日：2010-08-05

Applicant: Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

Inventor： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

IPC: H01L29/04 ,  H01L47/00

CPC classification number: H01L27/11507 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/24

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

Abstract translation: 提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。 第一电极层被部分地去除以在第一纳米线下方形成第一电极。 填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。 在第一纳米线和第一绝缘层上形成第二电极层。 多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。 使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。 还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

公开(公告)号：US08330155B2

公开(公告)日：2012-12-11

申请号：US12608130

申请日：2009-10-29

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/7869

Abstract: Semiconductor devices include a gate electrode, a gate insulation layer, a first channel layer pattern, a second channel layer pattern and first and second metallic patterns. The gate electrode is on a substrate. The gate insulation layer is on the gate electrode. The first channel layer pattern is on the gate insulation layer, and has a first conductivity level. The second channel layer pattern is on the first channel layer pattern, and has a second conductivity level that is lower than the first conductivity level. The first and second metallic patterns are on the gate insulation layer and contact respective sidewalls of the first and second channel layer patterns.

Abstract translation: 半导体器件包括栅电极，栅极绝缘层，第一沟道层图案，第二沟道层图案以及第一和第二金属图案。 栅电极在基板上。 栅极绝缘层位于栅电极上。 第一沟道层图案在栅极绝缘层上，并且具有第一导电性水平。 第二沟道层图案在第一沟道层图案上，并且具有低于第一导电率水平的第二导电率水平。 第一和第二金属图案在栅极绝缘层上并且接触第一和第二沟道层图案的相应侧壁。

公开(公告)号：US07994557B2

公开(公告)日：2011-08-09

申请号：US12781907

申请日：2010-05-18

Applicant: In-Gyu Baek ,  Moon-Sook Lee

Inventor： In-Gyu Baek ,  Moon-Sook Lee

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L27/115 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

Abstract translation: 提供了使用过渡金属氧化物层作为数据存储材料层的非易失性存储单元。 非易失性存储单元包括彼此重叠的下电极和上电极。 在下电极和上电极之间设置过渡金属氧化物层图案。 过渡金属氧化物层图案由化学式MxOy表示。 在化学式中，字母“M”，“O”，“x”和“y”分别表示过渡金属，氧，过渡金属组成和氧组成。 与稳定的过渡金属氧化物层图案相比，过渡金属氧化物层图案具有过量的过渡金属含量。 还提供了制造非易失性存储单元的方法。

公开(公告)号：US20100200831A1

公开(公告)日：2010-08-12

申请号：US12656634

申请日：2010-02-05

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L45/12 ,  H01L45/1233

Abstract: Non-volatile memory devices including a lower electrode formed on a substrate; an active memory material formed on the lower electrode; an upper electrode formed on the active memory material; and an adhesive layer formed in part of a region between the active memory material and the upper electrode.

Abstract translation: 包括形成在基板上的下电极的非易失性存储器件; 形成在下电极上的有源记忆材料; 形成在所述有源记忆材料上的上电极; 以及在活性记录材料和上部电极之间的区域的一部分中形成的粘合剂层。

公开(公告)号：US20100013018A1

公开(公告)日：2010-01-21

申请号：US12506656

申请日：2009-07-21

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L27/092

CPC classification number: H01L27/124 ,  B82Y10/00 ,  H01L27/095 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/45 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/7869

Abstract: In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.

Abstract translation: 在互补金属氧化物半导体（CMOS）晶体管及其制造方法中，在基板上设置具有第一导电类型的半导体沟道材料。 具有第一导电类型的第一晶体管和具有第二导电类型的第二晶体管分别位于衬底上。 第一晶体管包括位于通道材料的第一表面上的第一栅极，该第一栅极通过栅极绝缘层的介质和位于沟道材料的第二表面上的一对欧姆触点，并且跨越第一栅电极的两侧部分 ， 分别。 第二晶体管包括通过栅极绝缘层的介质定位在沟道材料的第一表面上的第二栅极和位于沟道材料的第二表面上并与第二栅电极的两侧部分交叉的一对肖特基触点 ， 分别。

公开(公告)号：US20100006849A1

公开(公告)日：2010-01-14

申请号：US12497852

申请日：2009-07-06

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L27/1292 ,  H01L29/42384

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract translation: 薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。 源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。 源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。 漏极线可以与沟道层接触并且可以与源极线隔开通道长度。 漏极线可以具有与源极线对称的结构。 可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

公开(公告)号：US07639521B2

公开(公告)日：2009-12-29

申请号：US11378945

申请日：2006-03-17

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: G11C11/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US20090189152A1

公开(公告)日：2009-07-30

申请号：US12354990

申请日：2009-01-16

Applicant: Byeong-Ok Cho ,  Moon-Sook Lee ,  Man-Hyoung Ryoo ,  Jung-Hyeon Kim ,  Takahiro Yasue

Inventor： Byeong-Ok Cho ,  Moon-Sook Lee ,  Man-Hyoung Ryoo ,  Jung-Hyeon Kim ,  Takahiro Yasue

IPC: H01L51/00 ,  H01L29/76

CPC classification number: H01L29/78391 ,  B82Y10/00 ,  G11C11/22 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684

Abstract: Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.

Abstract translation: 提供了一种铁电存储器件。 铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体 介于无机通道图案和栅电极之间的层。

公开(公告)号：US20090137091A1

公开(公告)日：2009-05-28

申请号：US12313887

申请日：2008-11-25

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/813 ,  Y10S977/842 ,  Y10S977/843 ,  Y10S977/89 ,  Y10S977/891

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract translation: 多个纳米线在与第一基板垂直的第一方向上在第一基板上生长。 覆盖纳米线的绝缘层形成在第一基板上，以限定包括纳米线和绝缘层的纳米线块。 移动纳米线块，使得每个纳米线沿平行于第一基底的第二方向排列。 绝缘层被部分去除以部分地暴露纳米线。 形成覆盖暴露的纳米线的栅极线。 将杂质注入到与栅极线相邻的纳米线的部分中。

公开(公告)号：US07374953B2

公开(公告)日：2008-05-20

申请号：US11202985

申请日：2005-08-12

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/00 ,  H01L21/8242 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract translation: 铁电随机存取存储器（FRAM）在衬底上包括半导体衬底和层间绝缘层。 扩散防止层在层间绝缘层上。 扩散防止层和层间绝缘层在其中形成有两个节点接触孔。 节点导电层图案分别与节点接触孔对准，并且设置成从扩散防止层向上突出。 下电极分别设置在覆盖节点导电层图案的扩散防止层上。 下部电极的厚度从从节点导电层图案的上表面朝向扩散防止层延伸的线逐渐减小。