公开(公告)号：US20080180984A1

公开(公告)日：2008-07-31

申请号：US11968829

申请日：2008-01-03

申请人： Daisaburo TAKASHIMA ,  Ryu Ogiwara

发明人： Daisaburo TAKASHIMA ,  Ryu Ogiwara

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned on, data retained in the sense amplifiers are capable of being written to the memory cells during the same time period substantially.

摘要翻译： 公开了一种包括铁电电容器的半导体存储器。 每个包括铁电电容器和绝缘栅型单元晶体管的存储单元连接到相应的位线。 绝缘栅型分离晶体管分别连接在多个位线选择晶体管和多个读出放大器之间。 当分离晶体管导通时，保持在读出放大器中的数据能够在相同的时间段内基本上被写入存储器单元。

公开(公告)号：US20070274138A1

公开(公告)日：2007-11-29

申请号：US11684183

申请日：2007-03-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5002

摘要： In this reference voltage generating circuit, the first current generating circuit generates the first constant current irrespective of the power supply voltage, when temperature is constant. When temperature changes, the magnitude of the first current changes according to the change. The second current generating circuit generates a second current depending on the power supply voltage. An output circuit outputs the output voltage. It has a resistor element for flowing the third current as an addition of the first current and the second current. An output voltage is output by the voltage drop of this resistor element.

摘要翻译： 在该参考电压产生电路中，当温度恒定时，第一电流产生电路产生与电源电压无关的第一恒定电流。 当温度变化时，第一电流的大小根据变化而变化。 第二电流产生电路根据电源电压产生第二电流。 输出电路输出输出电压。 它具有用于使第三电流作为第一电流和第二电流的相加的电阻元件。 输出电压由该电阻元件的电压降输出。

公开(公告)号：US20070241736A1

公开(公告)日：2007-10-18

申请号：US11783039

申请日：2007-04-05

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147 ,  G11C7/04

摘要： A reference voltage generator circuit comprises a first current path and a second current path. The first current path is formed between an input terminal supplied with a first reference voltage and an output terminal and including a first diode and a first resistor serially connected from the input terminal. The second current path is formed between the input terminal and the output terminal and including a second diode, a second resistor and a third resistor serially connected from the input terminal. A comparator is supplied with a voltage on a node between the first diode and the first resistor and a voltage on a node between the second resistor and the third resistor for comparative amplification. A transistor is connected between the output terminal and a second reference voltage and having a control terminal to receive an output from the first comparator.

摘要翻译： 参考电压发生器电路包括第一电流路径和第二电流路径。 第一电流路径形成在提供有第一参考电压的输入端子和输出端子之间，并且包括第一二极管和从输入端子串联连接的第一电阻器。 第二电流路径形成在输入端子和输出端子之间，并且包括从输入端子串联连接的第二二极管，第二电阻器和第三电阻器。 比较器在第一二极管和第一电阻之间的节点上提供电压，并且在第二电阻器和第三电阻器之间的节点上的电压用于比较放大。 晶体管连接在输出端和第二参考电压之间，并且具有用于接收来自第一比较器的输出的控制端。

公开(公告)号：US07142473B2

公开(公告)日：2006-11-28

申请号：US11059569

申请日：2005-02-17

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Michael Jacob

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C11/22

摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

摘要翻译： 半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。 位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。 参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。 参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。 读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。

公开(公告)号：US07057917B2

公开(公告)日：2006-06-06

申请号：US10743906

申请日：2003-12-24

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US07046541B2

公开(公告)日：2006-05-16

申请号：US10830046

申请日：2004-04-23

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first and second electrodes. A first bit line is electrically connected to the first electrode. A first potential generation circuit supplies a first potential to the second electrode to apply a voltage which drops at a first rate of change with a rise of temperature to the ferroelectric capacitor. A sense amplifier amplifies a potential difference between the first bit line and a second bit line complementary to the first bit line.

摘要翻译： 公开了一种半导体集成电路器件，包括存储单元阵列，该存储单元阵列包括具有第一和第二电极的铁电电容器的存储单元。 第一位线电连接到第一电极。 第一电位产生电路向第二电极提供第一电位，以施加以第一变化率下降的电压随着温度上升到铁电电容器。 读出放大器放大第一位线和与第一位线互补的第二位线之间的电位差。

公开(公告)号：US06980460B2

公开(公告)日：2005-12-27

申请号：US10803935

申请日：2004-03-19

申请人： Shinichiro Shiratake ,  Ryu Ogiwara

发明人： Shinichiro Shiratake ,  Ryu Ogiwara

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes first and second bit lines (BLs), first and second plate lines (PLs), a first series connected TC unit type structure connected between the first BL and the first PL, a second series connected TC unit type structure connected between the second BL and the second PL, a PL potential control circuit, and a BL potential control circuit. The PL potential control circuit controls a potential of the first PL from a first potential to a second potential and a potential of the second PL from the first potential to a third potential, when the first series connected TC unit type structure is selected. The BL potential control circuit controls a potential of the second BL to the third potential, after charges are transferred from the first series connected TC unit type structure to the first BL.

公开(公告)号：US20050057956A1

公开(公告)日：2005-03-17

申请号：US10803935

申请日：2004-03-19

申请人： Shinichiro Shiratake ,  Ryu Ogiwara

发明人： Shinichiro Shiratake ,  Ryu Ogiwara

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes first and second bit lines (BLs), first and second plate lines (PLs), a first series connected TC unit type structure connected between the first BL and the first PL, a second series connected TC unit type structure connected between the second BL and the second PL, a PL potential control circuit, and a BL potential control circuit. The PL potential control circuit controls a potential of the first PL from a first potential to a second potential and a potential of the second PL from the first potential to a third potential, when the first series connected TC unit type structure is selected. The BL potential control circuit controls a potential of the second BL to the third potential, after charges are transferred from the first series connected TC unit type structure to the first BL.

摘要翻译： 一种半导体集成电路器件，包括第一和第二位线（BL），第一和第二板线（PL），连接在第一BL和第一PL之间的第一串联连接的TC单元型结构，第二串联连接的TC单元型结构 连接在第二BL和第二PL之间，PL电位控制电路和BL电位控制电路。 当选择第一串联连接的TC单元型结构时，PL电位控制电路控制第一PL从第一电位到第二电位的电位和第二PL的电位从第一电位到第三电位。 在电荷从第一串联连接的TC单元型结构转移到第一BL之后，BL电位控制电路控制第二BL的电位到第三电位。

公开(公告)号：US5418750A

公开(公告)日：1995-05-23

申请号：US200107

申请日：1994-02-22

申请人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

发明人： Shinichiro Shiratake ,  Takehiro Hasegawa ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Ryo Fukuda

IPC分类号： G11C11/407 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.

摘要翻译： 半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取 连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于 选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管 第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组 第一位线组以相反的方向规则地布置。

公开(公告)号：US08531901B2

公开(公告)日：2013-09-10

申请号：US13196417

申请日：2011-08-02

申请人： Ryu Ogiwara ,  Hitoshi Iwai ,  Kiyotaro Itagaki

发明人： Ryu Ogiwara ,  Hitoshi Iwai ,  Kiyotaro Itagaki

IPC分类号： G11C7/02

CPC分类号： G11C16/30 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.

摘要翻译： 半导体存储器件包括单元阵列，电压产生电路和控制电路。 单元阵列包括存储单元串。 电压产生电路布置在电池阵列的下方。 每个存储单元串包括半导体层，控制栅极和存储单元晶体管。 半导体层包括一对柱部和连接部。 控制门与柱部相交。 存储单元晶体管形成在柱部分和控制栅极的交点处。 在写入操作和读取操作中，控制电路不驱动对作为写入目标和读取目标的存储单元串产生噪声的电压产生电路，并且驱动不对存储器单元串产生噪声的电压产生电路作为 写目标和读目标。