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    NFC APPARATUS CAPABLE TO PERFORM A CONTACTLESS TAG READING FUNCTION
    61.
    发明申请
    NFC APPARATUS CAPABLE TO PERFORM A CONTACTLESS TAG READING FUNCTION 有权
    NFC设备能够执行无缝标签读取功能

    公开(公告)号：US20140022060A1

    公开(公告)日：2014-01-23

    申请号：US13944169

    申请日：2013-07-17

    Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Juergen BOEHLER ,  Alexandre CHARLES

    IPC: H04B5/00

    CPC classification number: H04B5/0056 ,  H04L63/0492 ,  H04M1/7253 ,  H04M2250/04 ,  H04W4/80 ,  H04W12/02

    Abstract: An NFC device may include a first and second controller interfaces, a first communication channel coupled to the first controller interface, and a second communication channel connected to the second controller interface. A secure element may include a secure element interface connected to the first communication channel and encryption/decryption circuitry configured to encrypt data to be sent on the first communication channel for being framed into the encrypted frames and to decrypt encrypted data extracted from the encrypted frames and received from the first communication channel. The secure element may also include management circuitry configured to control the encryption/decryption circuitry for managing the encrypted communication with the NFC controller. A device host may include a host device interface coupled to the second controller interface and control means or circuitry configured to control the management circuitry through non-encrypted commands exchanged on the first and second communication channels.

    Abstract translation: NFC设备可以包括第一和第二控制器接口，耦合到第一控制器接口的第一通信信道和连接到第二控制器接口的第二通信信道。 安全元件可以包括连接到第一通信信道的安全元件接口和加密/解密电路，所述加密/解密电路被配置为加密要在第一通信信道上发送的数据，以被成帧为加密的帧，并解密从加密的帧中提取的加密数据， 从第一个通信频道接收。 安全元件还可以包括配置成控制加密/解密电路以管理与NFC控制器的加密通信的管理电路。 设备主机可以包括耦合到第二控制器接口的主机设备接口和被配置为通过在第一和第二通信信道上交换的非加密命令来控制管理电路的控制装置或电路。

    Configurable cryptographic processor with integrated DMA interface for secure data handling
    62.
    发明授权
    Configurable cryptographic processor with integrated DMA interface for secure data handling 有权

    公开(公告)号：US12117949B2

    公开(公告)日：2024-10-15

    申请号：US18364786

    申请日：2023-08-03

    Applicant: STMicroelectronics Application GMBH

    Inventor： Rolf Nandlinger ,  Roberto Colombo

    IPC: G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06F13/42 ,  G06F21/60 ,  G06F21/72

    CPC classification number: G06F13/28 ,  G06F9/30105 ,  G06F9/3877 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/72

    Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

    Processing system, related integrated circuit, device and method
    65.
    发明授权
    Processing system, related integrated circuit, device and method 有权

    公开(公告)号：US11915008B2

    公开(公告)日：2024-02-27

    申请号：US17654537

    申请日：2022-03-11

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

    Inventor： Roberto Colombo ,  Nicolas Bernard Rene Grossier ,  Fabio Enrico Carlo Disegni

    IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/30

    CPC classification number: G06F9/4403 ,  G06F9/30101

    Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

    Processing system, related integrated circuit, device and method
    66.
    发明授权
    Processing system, related integrated circuit, device and method 有权

    公开(公告)号：US11822934B2

    公开(公告)日：2023-11-21

    申请号：US17341054

    申请日：2021-06-07

    Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Roberto Colombo ,  Om Ranjan

    IPC: G06F11/10 ,  G06F9/445 ,  G06F13/36 ,  H04L9/06 ,  H04L9/32

    CPC classification number: G06F9/44505 ,  G06F11/1004 ,  G06F13/36 ,  H04L9/0643 ,  H04L9/3247

    Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.

    Processing system, related integrated circuit, device and method
    67.
    发明授权
    Processing system, related integrated circuit, device and method 有权

    公开(公告)号：US11764807B2

    公开(公告)日：2023-09-19

    申请号：US17858782

    申请日：2022-07-06

    Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

    Inventor： Vivek Mohan Sharma ,  Roberto Colombo

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1105 ,  H03M13/611

    Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.

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