公开(公告)号：US12256851B2

公开(公告)日：2025-03-25

申请号：US17940821

申请日：2022-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon Park ,  Seungjoon Lee ,  Yeeun Choi ,  Hoon Han

IPC: A47F10/06 ,  A47B31/00 ,  G01C21/20 ,  G06Q10/083

Abstract: Provided is an electronic device configured to generate a route including a point of departure and a first destination determined based on order information, while the electronic device is moved along the route using a driver, in response to not receiving an order from the first destination on which seating information indicating at least one seated customer is identified, perform an operation of outputting information indicating a serving tray accommodating a basic item based on the electronic device reaching the first destination, and based on a drive along the route being completed, in response to not delivering, to the first destination, at least one item indicated in an order received from the first destination, exclude the first destination from the route.

公开(公告)号：US20250098355A1

公开(公告)日：2025-03-20

申请号：US18444062

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Weizhong ZHOU

IPC: H01L27/146

Abstract: A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a substrate; a chip spaced from the substrate and having a first surface, a second surface and a side surface, the first surface of the chip including a photosensitive area and a non-photosensitive area surrounding the photosensitive area; a molding layer having a first surface and a second surface, the molding layer provided on the non-photosensitive area of the chip and the side surface of the chip.

公开(公告)号：US20250098324A1

公开(公告)日：2025-03-20

申请号：US18586112

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes: 1st source/drain regions connected through a 1st channel structure which is controlled by a 1st gate structure; and a 2nd source/drain regions, respectively above the 1st source/drain regions, connected through a 2nd channel structure which is controlled by a 2nd gate structure, wherein the 1st channel structure and the 2nd channel structure comprise different materials.

公开(公告)号：US20250098278A1

公开(公告)日：2025-03-20

申请号：US18815956

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho Moon ,  Donghoon Hwang ,  Hyojin Kim ,  Kyunghee Cho

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in the first direction, upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction, a middle dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers, a lower gate structure on the lower channel layers; an upper gate structure on the upper channel layers on the lower gate structure and extending in a second direction perpendicular to the first direction. a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the middle dielectric isolation structure, and extending around the lower gate structure.

公开(公告)号：US20250098201A1

公开(公告)日：2025-03-20

申请号：US18961728

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Sunkyu HWANG ,  Jongseob KIM ,  Joonyong KIM ,  Woochul JEON

IPC: H01L29/778 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

公开(公告)号：US20250098176A1

公开(公告)日：2025-03-20

申请号：US18608130

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KILHO LEE

IPC: H10B61/00

Abstract: A magnetic memory device may include conductive lines provided in cell region and peripheral region, a first insulating layer provided in the cell region and the peripheral region, and surrounding the conductive lines, a second insulating layer provided on the first insulating layer in the cell region and the peripheral region, and on top surfaces of the conductive lines, and data storage patterns provided on the second insulating layer in the cell region and electrically connected to corresponding conductive lines of the conductive lines. The second insulating layer in the peripheral region may include first portions on the top surfaces of the conductive lines, and second portions disposed between the first portions. Top surfaces of the first portions may be disposed at a level higher than top surfaces of the second portions.

公开(公告)号：US20250098171A1

公开(公告)日：2025-03-20

申请号：US18885031

申请日：2024-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghun KIM ,  Hoseok HEO ,  Sunho KIM ,  Seungyeul YANG ,  Minhyun LEE ,  Seokhoon CHOI

IPC: H10B43/30 ,  H10B43/27

Abstract: A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.

公开(公告)号：US20250098170A1

公开(公告)日：2025-03-20

申请号：US18968053

申请日：2024-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming a mold structure, in which sacrificial layers and insulating layers are alternately stacked, on a substrate; forming trenches to penetrate the mold structure; forming first sacrificial patterns in the trenches; forming a first supporting layer on the mold structure and the first sacrificial patterns; forming vertical structures to penetrate the first supporting layer and the mold structure; forming a second supporting layer on the first supporting layer and on the vertical structures; forming openings to penetrate the first and second supporting layers and to expose the first sacrificial patterns; removing the first sacrificial patterns through the openings; and replacing the sacrificial layers with electrodes.

公开(公告)号：US20250098155A1

公开(公告)日：2025-03-20

申请号：US18742376

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsung Kang ,  Hyoungyol Mun ,  Youngmin Lee

IPC: H10B12/00

Abstract: A semiconductor device includes lower electrodes on a substrate, a support pattern between the lower electrodes, an upper electrode on the lower electrodes and the support pattern, and a dielectric layer between the lower electrodes and the upper electrode, and between the support pattern and the upper electrode. The upper electrode includes a first portion on upper surfaces of the lower electrodes and a second portion on a sidewall of the support pattern. The first portion is thicker than the second portion.

公开(公告)号：US20250098146A1

公开(公告)日：2025-03-20

申请号：US18815974

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun Lee ,  Kiseok Lee ,  Huijung Kim ,  Younggeun Song ,  Yongjin Lee

IPC: H10B12/00

Abstract: A semiconductor device includes bit lines, channels, a first capping pattern, a gate insulation pattern, a gate electrode and capacitors. The bit lines are on a substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in a second direction. The channels are spaced apart from each other in the first direction. The first capping pattern is on a sidewall of each of the channels. The gate insulation pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulation pattern. The capacitors are electrically connected to respective ones of the channels.