公开(公告)号：US6020621A

公开(公告)日：2000-02-01

申请号：US14868

申请日：1998-01-28

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76235

Abstract: A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with the semiconductor substrate at edge of the recessed region. The trench isolation further includes a second insulator layer filling within the recessed region over the first insulator. As a preferred embodiment, the recessed region can have well rounded corners at bottom and abutting top surface of the semiconductor substrate. The first insulator has inwardly increased height after the planarization process. The second insulator layer aligns with the first insulator at inner edge of the first insulator. The second insulator layer can also have a top plain region.

Abstract translation: 提供半导体衬底中的沟槽隔离。 沟槽隔离包括半导体衬底中的凹陷区域。 沟槽隔离还具有衬在凹陷区域上的第一绝缘体层。 第一绝缘体与凹陷区域的边缘处的半导体衬底对准。 沟槽隔离还包括填充在第一绝缘体之上的凹陷区域内的第二绝缘体层。 作为优选实施例，凹陷区域可以在半导体衬底的底部和邻接的顶表面处具有良好的圆角。 第一绝缘体在平坦化处理之后具有向内增加的高度。 第二绝缘体层与第一绝缘体在第一绝缘体的内边缘处对准。 第二绝缘体层也可以具有顶部平坦区域。

公开(公告)号：US6010934A

公开(公告)日：2000-01-04

申请号：US33527

申请日：1998-03-02

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/308 ,  H01L21/335 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/336

CPC classification number: B82Y10/00 ,  H01L21/76243 ,  H01L21/823437 ,  H01L29/66439 ,  H01L21/3086 ,  Y10S438/947 ,  Y10S977/937

Abstract: A method of making nanometer Si islands for single electron transistors is disclosed. Initially, a pad oxide is deposited over a silicon substrate. Oxygen ions are implanted into the silicon substrate to form an oxygen amorphized region and a high-temperature annealing is performed to form a buried oxide layer in the silicon substrate. Then, a thermal silicon oxide is formed to reduce the thickness of the silicon substrate on the buried oxide layer. The thermal oxide is removed and an ultra-thin oxide layer is then formed on the silicon substrate. A plurality of silicon nitride blocks is formed on the ultra-thin silicon oxide. Afterwards, the spacers of the silicon nitride blocks are formed. The silicon nitride blocks are removed by using wet etching technique. The ultra-thin silicon oxide is etched back and the polysilicon spacers are used as hard mask to Si substrate to form a plurality of nanometer silicon islands. The ultra-thin silicon oxide is removed and an ultra-thin oxynitride layer is regrown on the nanometer silicon islands. Finally, a n+ polysilicon layer is conformally deposited onto the silicon substrate and the nanometer silicon islands.

Abstract translation: 公开了制造用于单电子晶体管的纳米Si岛的方法。 最初，在硅衬底上沉积衬垫氧化物。 将氧离子注入到硅衬底中以形成氧非晶区，并且进行高温退火以在硅衬底中形成掩埋氧化物层。 然后，形成热氧化硅以减小掩埋氧化物层上的硅衬底的厚度。 去除热氧化物，然后在硅衬底上形成超薄氧化层。 在超薄氧化硅上形成多个氮化硅块。 之后，形成氮化硅块的间隔物。 通过使用湿蚀刻技术去除氮化硅块。 将超薄氧化硅回蚀刻，多晶硅间隔物用作Si衬底的硬掩模以形成多个纳米硅岛。 去除超薄氧化硅，并在纳米硅岛上重新生长超薄氧氮化物层。 最后，n +多晶硅层共形沉积到硅衬底和纳米硅岛上。

公开(公告)号：US5998264A

公开(公告)日：1999-12-07

申请号：US266552

申请日：1999-03-11

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/66825 ,  H01L21/28194 ,  H01L21/28211

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride. A conductive layer to serve as control gate is subsequently formed on the high k dielectric layer. A patterning technique is used to pattern the layers.

Abstract translation: 本发明的方法包括图案化栅极结构。 然后，在栅极结构的侧壁上形成多
氧化物层。 然后，在栅极结构的侧壁上形成氮化硅侧壁间隔物。 然后，制造器件的源极/漏极结构。 接下来，去除侧壁间隔物以暴露源和漏的一部分。 然后，在栅极结构的表面，氧化物层和暴露的源极和漏极上形成未掺杂的非晶硅层。 使用干式氧化工艺将非晶硅层转变成在衬底和氧化物的界面处的纹理化隧道氧化物。 形成多晶硅层，然后进行化学机械抛光。 在多晶硅层上形成导电层。 随后，在导电层上形成通过喷射气相沉积（JVD）沉积的氮化硅层。 接下来在JVD氮化物上形成高k电介质层。 随后在高k电介质层上形成用作控制栅极的导电层。 使用图案化技术对层进行图案化。

公开(公告)号：US5994747A

公开(公告)日：1999-11-30

申请号：US23454

申请日：1998-02-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L29/66636 ,  H01L29/665 ,  H01L29/7834

Abstract: The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon oxynitride layer is formed on the side walls of the gate and refilled into the undercut portions to be used as a portion of the gate oxide. Side wall spacers are formed on the side walls of the gate. A polycide layer is formed at the top of the gate to reduce the electrical resistance. Source and drain regions are formed in the recessed portions of the substrate. Lightly doped drain (LDD) structures are formed in the substrate adjacent to the gate and under the gate oxide. Extended source and drain are formed between the source and drain and the LDD structure to suppress the short channel effect. Self-aligned silicide (SALICIDE) layers are formed at top of the source and drain.

Abstract translation: 本发明包括栅极氧化物。 栅极形成在栅极氧化物上。 在门下方形成底切部分。 基板具有与栅极相邻的凹部。 在栅极的侧壁上形成氮氧化硅层，并重新填充到底切部分中以用作栅极氧化物的一部分。 侧壁隔板形成在门的侧壁上。 在栅极的顶部形成多晶硅化物层以降低电阻。 源极和漏极区域形成在衬底的凹陷部分中。 在与栅极相邻的衬底中和栅极氧化物下方形成轻掺杂漏极（LDD）结构。 在源极和漏极之间形成扩展的源极和漏极，并且LDD结构以抑制短沟道效应。 在源极和漏极的顶部形成自对准硅化物（SALICIDE）层。

公开(公告)号：US5976967A

公开(公告)日：1999-11-02

申请号：US23261

申请日：1998-02-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76807 ,  H01L21/7684

Abstract: The method of metallization includes the steps as follows. At first, a semiconductor substrate is provided and a dielectric layer is formed over the semiconductor substrate. A portion of the dielectric layer is removed to form contact holes and a first conductive layer is formed within the contact holes and over the dielectric layer. A portion of the first conductive layer is removed to define a contact pattern. Using the first conductive layer as a mask, a portion of the dielectric layer is removed to form openings within the dielectric layer and over the first conductive layer. A second conductive layer is then formed within the openings and over the first conductive layer. To planarize the surface of the semiconductor substrate, a portion of the second conductive layer and the first conductive layer is removed to planarize to the dielectric layer.

Abstract translation: 金属化方法包括以下步骤。 首先，提供半导体衬底，并在半导体衬底上形成电介质层。 去除介电层的一部分以形成接触孔，并且在接触孔内和介电层上方形成第一导电层。 去除第一导电层的一部分以限定接触图案。 使用第一导电层作为掩模，去除介电层的一部分以在介电层内和第一导电层上形成开口。 然后在开口内和第一导电层上形成第二导电层。 为了平坦化半导体衬底的表面，去除第二导电层和第一导电层的一部分以平坦化到电介质层。

公开(公告)号：US5972761A

公开(公告)日：1999-10-26

申请号：US998796

申请日：1997-12-29

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66545

Abstract: This invention proposes a new process to form MOS transistor with a gate-side air-gap structure and an extension ultra-shallow S/D junction for high speed devices. After growing the thin gate oxide film on silicon substrate, a stacked-amorphous-Si (SAA) film is deposited. A thin CVD oxide film is deposited and then patterned. The top two amorphous-Si layers are etched back and then form the nitride spacers. The pad CVD oxide film is removed by diluted HF solution followed by S/D/G implant. High temperature thermal oxidation process is used to convert the bottom amorphous-Si layers outside the nitride spacers into thermal oxide and simultaneously to form shallow junction. The nitride spacers are removed and then the low energy/high dose ion implantation is performed for extension S/D junction. The bottom amorphous-Si layer is etched back and then RTP anneal in N.sub.2 O or NO ambient is used to recover the etching damage to form an extension S/D junction. A thick CVD oxide film is deposited on all regions. Due to the step coverage issue, a air-gap structure would be formed at the gate side.

Abstract translation: 本发明提出了一种用于形成用于高速器件的具有栅极侧气隙结构和扩展超浅S / D结的MOS晶体管的新工艺。 在硅衬底上生长薄栅氧化膜之后，沉积堆积的非晶Si（SAA）膜。 沉积薄的CVD氧化膜，然后进行图案化。 顶部的两个非晶硅层被回蚀，然后形成氮化物间隔物。 通过稀释的HF溶液，随后S / D / G植入物去除衬垫CVD氧化膜。 高温热氧化工艺用于将氮化物间隔层外部的底部非晶硅层转化为热氧化物，同时形成浅结。 去除氮化物间隔物，然后对扩展S / D结进行低能量/高剂量离子注入。 底部非晶硅层被回蚀，然后使用N2O或NO环境中的RTP退火来恢复蚀刻损伤以形成延伸S / D结。 在所有区域上沉积厚的CVD氧化膜。 由于台阶覆盖问题，闸门侧将形成气隙结构。

公开(公告)号：US5963802A

公开(公告)日：1999-10-05

申请号：US14865

申请日：1998-01-28

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238

CPC classification number: H01L21/823892

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract translation: 本发明提出了一种用于形成CMOS器件的平面化双阱的工艺。 在沉积衬垫氧化物和氮化硅层之后，通过使用光致抗蚀剂作为掩模来执行高能磷离子注入以形成N阱。 然后通过液相沉积工艺沉积的厚氧化物层然后在氮化硅层的N阱区域部分上生长，但不在光致抗蚀剂上生长。 在剥离光致抗蚀剂之后，通过使用LPD氧化物层作为掩模，进行高能量硼离子注入以形成P阱。 厚的LPD氧化物层被BOE或HF溶液除去。 进行高温蒸汽氧化以生长场氧化物。 在该步骤中，掺杂剂被激活并被驱动以形成双井。 在去除衬垫氧化物和氮化硅层之后，通过标准工艺制造CMOS器件。

公开(公告)号：US5930617A

公开(公告)日：1999-07-27

申请号：US48154

申请日：1998-03-25

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/6653 ,  H01L21/28052 ,  H01L21/28247 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/66545

Abstract: The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as an anti-reflective coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the oxide layer are patterned to form ultra short channel polysilicon gates. A thermal annealing is performed to recover the etching damage in the substrate and generate a pad oxide layer on the surface of the polysilicon gate and the substrate. An nitrogen-doped amorphous silicon layer is formed on the gate structure and on the pad oxide. Next, an ion implantation is carried out to dope dopants into the gate and substrate, thereby forming source and drain. A steam oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon dioxide layer. Simultaneously, an ultra-shallow extended source and drain junction adjacent to the gate structure is obtained by using the amorphous silicon layer as a diffusion source. Subsequently, the nitrogen-doped silicon dioxide layer is etched back to form oxide spacers. Then, the cap silicon nitride layer are removed. Then, two-step silicidation process are used to form silicided contacts.

Abstract translation: 本发明包括在基板上形成氧化物层。 通过化学气相沉积在栅极氧化物层上沉积未掺杂的多晶硅层。 接下来，在多晶硅层上依次形成氮化硅层，作为抗反射涂层（ARC）。 然后，对未掺杂的多晶硅层，ARC层和氧化物层进行构图以形成超短沟道多晶硅栅极。 进行热退火以恢复基板中的蚀刻损伤，并在多晶硅栅极和基板的表面上产生焊盘氧化物层。 在栅极结构和衬底氧化物上形成氮掺杂非晶硅层。 接下来，进行离子注入以将掺杂剂掺杂到栅极和衬底中，从而形成源极和漏极。 进行蒸汽氧化以将氮掺杂的非晶硅层转换成氮掺杂的热二氧化硅层。 同时，通过使用非晶硅层作为扩散源，获得与栅极结构相邻的超浅扩展源极和漏极结。 随后，氮掺杂二氧化硅层被回蚀以形成氧化物间隔物。 然后，去除盖子氮化硅层。 然后，使用两步硅化工艺形成硅化物接触。

公开(公告)号：US5909620A

公开(公告)日：1999-06-01

申请号：US988031

申请日：1997-12-10

Applicant: Shye Lin Wu

Inventor： Shye Lin Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: This invention discloses a novel design to fabricate a ring-like capacitor in a semiconductor memory device for increasing the area of the capacitor electrodes. The ring-like conductive structure of the electrode of the capacitor includes a mushroom-shaped member having a flat-headed cap and a stem coupled to the source region of the semiconductor memory device, a solid cylindrical member disposed on the cap of the mushroom-shaped member, and a side-wall spacer being a hollow cylindrical member disposed on the cap of said mushroom-shaped member to increase the area of the capacitor electrodes thereby increasing the capacitance of the capacitor to provide a sufficient capacitance while maintaining high integration in semiconductor memory cells.

Abstract translation: 本发明公开了一种在半导体存储器件中制造环形电容器以增加电容器电极的面积的新颖设计。 电容器电极的环形导电结构包括具有平头帽和连接到半导体存储器件的源极区的杆的蘑菇状构件，设置在蘑菇状盖的盖上的实心圆柱形构件， 以及设置在所述蘑菇形构件的盖上的中空圆柱形构件的侧壁间隔件，以增加电容器电极的面积，从而增加电容器的电容以提供足够的电容，同时保持高半导体集成度 记忆细胞

公开(公告)号：US5897348A

公开(公告)日：1999-04-27

申请号：US42351

申请日：1998-03-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8234 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L21/823443 ,  H01L27/0266

Abstract: A method to fabricate simultaneously a CMOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The NMOS transistor and PMOS transistor in the portion of the CMOS transistor have both anti-punchthrough and salicide structures and individually with n-LDD and p-LDD structure, respectively. The structure of ESD protective devices is fabricated with self-aligned silicide but without LDD, thus the degradation of ESD protection can be solved. The problems of accumulative aberration in scaled devices can also be alleviated through using blanket ion implantation technology and salicide process to reduce the mask count as shown in the invention.

Abstract translation: 公开了一种同时制造硅衬底中的CMOS晶体管和ESD保护晶体管的方法。 CMOS晶体管中的NMOS晶体管和PMOS晶体管分别具有抗穿透和自对准结构，并分别具有n-LDD和p-LDD结构。 ESD保护器件的结构采用自对准硅化物，但不具有LDD，因此可以解决ESD保护的劣化。 如本发明所示，通过使用毯式离子注入技术和自对准处理来减少掩模计数，也可以减轻定标器件中的累积像差的问题。