Method and apparatus for executing host commands

    公开(公告)号:US11537328B2

    公开(公告)日:2022-12-27

    申请号:US17380402

    申请日:2021-07-20

    发明人: Po-Wei Wu

    IPC分类号: G06F3/06

    摘要: An apparatus and a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

    METHOD FOR ACCESSING FLASH MEMORY AND FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE THEREOF

    公开(公告)号:US20220405215A1

    公开(公告)日:2022-12-22

    申请号:US17463542

    申请日:2021-08-31

    摘要: Disclosed is a method for accessing data from a flash memory. The method comprises a flash memory controller receiving an access command from a host device, according to the access command, the flash memory accessing a plurality of data from the data pages of a plurality of blocks in the flash memory simultaneously and simultaneously temporarily storing the accessed data to the plurality of buffers of the flash memory, and simultaneously temporarily storing the data in the plurality of buffers of the flash memory buffer to the plurality of buffers the flash memory controller.

    Apparatus and method and computer program product for verifying memory interface

    公开(公告)号:US11506703B2

    公开(公告)日:2022-11-22

    申请号:US16548463

    申请日:2019-08-22

    发明人: Wei-Liang Sung

    IPC分类号: G01R31/28 G11C11/412 G06F3/06

    摘要: The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

    Flash memory controller, flash memory module and associated electronic device

    公开(公告)号:US11494085B2

    公开(公告)日:2022-11-08

    申请号:US17367438

    申请日:2021-07-05

    发明人: Tsung-Chieh Yang

    摘要: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

    MEMORY ADDRESSING METHODS AND ASSOCIATED CONTROLLER, MEMORY DEVICE AND HOST

    公开(公告)号:US20220350502A1

    公开(公告)日:2022-11-03

    申请号:US17865130

    申请日:2022-07-14

    发明人: Chao-Kuei HSIEH

    IPC分类号: G06F3/06 G06F12/06

    摘要: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

    Apparatus and method and computer program product for handling flash physical-resource sets

    公开(公告)号:US11449416B2

    公开(公告)日:2022-09-20

    申请号:US16732944

    申请日:2020-01-02

    发明人: Che-Wei Hsu

    摘要: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

    METHOD AND COMPUTER PROGRAM PRODUCT FOR PERFORMING DATA WRITES INTO A FLASH MEMORY

    公开(公告)号:US20220269600A1

    公开(公告)日:2022-08-25

    申请号:US17667801

    申请日:2022-02-09

    发明人: Kuo-Ting HUANG

    IPC分类号: G06F12/02 G06F12/10

    摘要: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

    Data Storage Device and Non-Volatile Memory Control Method

    公开(公告)号:US20220269443A1

    公开(公告)日:2022-08-25

    申请号:US17648679

    申请日:2022-01-24

    IPC分类号: G06F3/06

    摘要: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

    Apparatus and method for segmenting a data stream of a physical layer

    公开(公告)号:US11422813B2

    公开(公告)日:2022-08-23

    申请号:US16892686

    申请日:2020-06-04

    发明人: Han-Cheng Huang

    摘要: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

    Memory addressing methods and associated controller, memory device and host

    公开(公告)号:US11422717B2

    公开(公告)日:2022-08-23

    申请号:US17095118

    申请日:2020-11-11

    发明人: Chao-Kuei Hsieh

    IPC分类号: G06F3/06 G06F12/06

    摘要: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.