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    Method and apparatus for performing on-system phase-locked loop management in memory device
    61.
    发明授权
    Method and apparatus for performing on-system phase-locked loop management in memory device 有权

    公开(公告)号：US11784652B2

    公开(公告)日：2023-10-10

    申请号：US17878042

    申请日：2022-07-31

    Applicant: Silicon Motion, Inc.

    Inventor： Fu-Jen Shih

    IPC: H03L7/23 ,  H03L7/085 ,  H03L7/187 ,  G11C29/02

    CPC classification number: H03L7/235 ,  G11C29/028 ,  H03L7/085 ,  H03L7/187

    Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

    METHOD AND APPARATUS FOR CACHING ADDRESS MAPPING INFORMATION IN FLASH MEMORY BASED STORAGE DEVICE
    62.
    发明公开
    METHOD AND APPARATUS FOR CACHING ADDRESS MAPPING INFORMATION IN FLASH MEMORY BASED STORAGE DEVICE 审中-公开

    公开(公告)号：US20230289091A1

    公开(公告)日：2023-09-14

    申请号：US17693431

    申请日：2022-03-14

    Applicant: Silicon Motion, Inc.

    Inventor： Yi-Kai Pai

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

    Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

    Memory controller, test device and link identification method
    63.
    发明授权
    Memory controller, test device and link identification method 有权

    公开(公告)号：US11755439B2

    公开(公告)日：2023-09-12

    申请号：US17700514

    申请日：2022-03-22

    Applicant: Silicon Motion, Inc.

    Inventor： Cheng-Yu Lee ,  Te-Kai Wang

    IPC: G06F11/22 ,  G06F11/273 ,  G06F11/263

    CPC classification number: G06F11/2273 ,  G06F11/2284 ,  G06F11/263 ,  G06F11/2635 ,  G06F11/2733

    Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

    Data storage device and non-volatile memory control method
    66.
    发明授权
    Data storage device and non-volatile memory control method 有权

    公开(公告)号：US11748023B2

    公开(公告)日：2023-09-05

    申请号：US17025004

    申请日：2020-09-18

    Applicant: Silicon Motion, Inc.

    Inventor： Yu-Hsiang Chung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Power recovery for data storage devices with an efficient space trimming technology is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming code. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming code, information of medium-length trimming and information of long-length trimming are recognized from a storage area of the non-volatile memory. According to the trimming information for medium-length trimming, dummy mapping data is programmed to the H2F table. According to the trimming information for long-length trimming, a trimming bitmap (TBM) is rebuilt. Each bit in the TBM marks space trimming of a first length.

    Initialization methods and associated controller, memory device and host
    68.
    发明授权
    Initialization methods and associated controller, memory device and host 有权

    公开(公告)号：US11726686B2

    公开(公告)日：2023-08-15

    申请号：US17843691

    申请日：2022-06-17

    Applicant: SILICON MOTION INC.

    Inventor： Chao-Kuei Hsieh

    IPC: G06F3/06 ,  G06F13/42

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/4221 ,  G06F2213/0026

    Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

    Fractional frequency divider and flash memory controller
    69.
    发明授权
    Fractional frequency divider and flash memory controller 有权

    公开(公告)号：US11705907B2

    公开(公告)日：2023-07-18

    申请号：US17707992

    申请日：2022-03-30

    Applicant: Silicon Motion, Inc.

    Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

    IPC: H03K21/02 ,  H03K21/08 ,  H03K21/10 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/40

    CPC classification number: H03K21/026 ,  G06F1/3275 ,  H03K5/00006 ,  H03K21/10 ,  H03K21/406

    Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

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