公开(公告)号：US11550962B2

公开(公告)日：2023-01-10

申请号：US16867911

申请日：2020-05-06

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F12/16 ,  G06F12/14 ,  G06F11/00 ,  G06F21/74 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/70 ,  G06F21/53 ,  G06F12/1027 ,  G06F13/24

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US20220392999A1

公开(公告)日：2022-12-08

申请号：US17889106

申请日：2022-08-16

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/412 ,  H01L27/11 ,  H01L27/118

Abstract: A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.

公开(公告)号：US20220367442A1

公开(公告)日：2022-11-17

申请号：US17877534

申请日：2022-07-29

Applicant: Socionext Inc.

Inventor： Taro FUKUNAGA ,  Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/02

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

公开(公告)号：US20220359541A1

公开(公告)日：2022-11-10

申请号：US17872810

申请日：2022-07-25

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI ,  Shinichi MORIWAKI

IPC: H01L27/11

Abstract: Nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

公开(公告)号：US11496853B2

公开(公告)日：2022-11-08

申请号：US17377010

申请日：2021-07-15

Applicant: SOCIONEXT INC.

Inventor： Kai Kobayashi ,  Takeshi Fujita ,  Shuji Miyasaka

IPC: H04R5/02 ,  H04S7/00 ,  H04S1/00 ,  H04R3/04 ,  H04R5/04 ,  H04R3/12

Abstract: A sound signal processing device includes: a vocal remover which generates a first output signal based on first-channel and second-channel sound signals and a first coefficient indicating a vocal bandwidth to be removed; a surround sound processor which generates a second output signal by adding a surround sound effect to the first output signal; an amplifier which amplifies a signal at an amplification factor that is based on a second coefficient; a synthesizer which synthesizes the second output signal with one of the first-channel and second-channel sound signals, and synthesizes a signal that is the second output signal inverted with another one of the first-channel and second-channel sound signals; and a coefficient determination unit which sets the second coefficient such that the amplification factor, used when the vocal bandwidth to be removed is greater than a first bandwidth, is greater than the amplification factor for the first bandwidth.

公开(公告)号：US11455993B2

公开(公告)日：2022-09-27

申请号：US16810568

申请日：2020-03-05

Applicant: SOCIONEXT INC.

Inventor： Kotaro Esaki

IPC: G10L15/22 ,  G10L13/00 ,  G10L15/30

Abstract: An electronic device controlling system that provides an instruction via voice for an operation of a speech recognition-capable electronic device includes a control device and a voice output device capable of communicating with the control device. The control device includes a first input unit that receives, from an operator, a first input to which a first operation instruction for the speech recognition-capable electronic device is assigned; and a transmitter that, when the first input unit receives the first input, transmits, to the voice output device, first information for communication corresponding to the first operation instruction assigned to the first input. The voice output device includes a receiver that receives the first information for communication from the control device; and an output unit that, when the receiver receives the first information for communication, outputs a first voice for the first operation instruction based on the first information for communication.

公开(公告)号：US20220293634A1

公开(公告)日：2022-09-15

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

公开(公告)号：US20220255584A1

公开(公告)日：2022-08-11

申请号：US17570056

申请日：2022-01-06

Applicant: Socionext Inc.

Inventor： Koji KAMISUKI

IPC: H04B3/40 ,  H04B3/54 ,  H04B17/00 ,  H04B17/336

Abstract: A simulation device includes: a layout setting unit which sets a layout of a power line communication (PLC) network; a parameter setting unit which sets an electrical parameter of the PLC network; a simulation execution unit; and a result output unit which outputs an electrical property obtained by the simulation. The layout setting unit includes: an information obtaining unit which obtains structure information indicating a structure of a building where the PLC network is to be provided and position information of one or more elements included in the PLC network; and a display information output unit which displays, on a display unit that displays information that relates to the PLC network, a diagram that is based on the structure information, and displays at least a portion of the PLC network that is based on the position information such that the portion is superimposed on the diagram.

公开(公告)号：US20220246283A1

公开(公告)日：2022-08-04

申请号：US17726201

申请日：2022-04-21

Applicant: Socionext Inc.

Inventor： Naoto YONEDA ,  Masaya TAMAMURA ,  Naoto ADACHI ,  Hiroshi KISHI

IPC: G16H30/20 ,  A61B8/00 ,  H04W4/38

Abstract: An ultrasonic probe includes a probe configured to receive an ultrasonic wave, a plurality of wireless communication devices, and processing circuitry configured to assign identification information to ultrasonic image data generated based on the ultrasonic wave, for identifying the ultrasonic image data; and cause each of the plurality of wireless communication devices to transmit in parallel the ultrasonic image data having the identification information assigned, to a terminal device.

公开(公告)号：US20220230954A1

公开(公告)日：2022-07-21

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.