公开(公告)号：US20130146953A1

公开(公告)日：2013-06-13

申请号：US13316641

申请日：2011-12-12

Applicant: Kangguo Cheng ,  Thomas N. Adam ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Kangguo Cheng ,  Thomas N. Adam ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/105 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/13 ,  H01L28/10 ,  H01L29/8611 ,  H01L29/94

Abstract: An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.

Abstract translation: 通过在替换栅极HK / MG流中蚀刻ETSOI和BOX层，在其晶体管和电容器区域中分别形成ETSOI晶体管以及电容器，结二极管，堤端触点和电阻器的组合。 电容器和其他器件形成与ETSOI替代栅极CMOS流相兼容。 低电阻电容器电极可以获得高质量的电容器和器件。 虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

公开(公告)号：US20120295417A1

公开(公告)日：2012-11-22

申请号：US13109567

申请日：2011-05-17

Applicant: Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

Inventor： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

IPC: H01L21/20

CPC classification number: H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

Abstract: A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

Abstract translation: 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

公开(公告)号：US08263468B2

公开(公告)日：2012-09-11

申请号：US12766859

申请日：2010-04-24

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

Abstract translation: 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

公开(公告)号：US20110159655A1

公开(公告)日：2011-06-30

申请号：US13045679

申请日：2011-03-11

Applicant: Thomas N. Adam ,  Judson R. Holt ,  Thomas A. Wallner

Inventor： Thomas N. Adam ,  Judson R. Holt ,  Thomas A. Wallner

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

Abstract translation: 提供了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间​​的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域， 区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

公开(公告)号：US07769134B1

公开(公告)日：2010-08-03

申请号：US12372104

申请日：2009-02-17

Applicant: Thomas N. Adam ,  Eric C. Harley ,  Anita Madan ,  Teresa L. Pinto

Inventor： Thomas N. Adam ,  Eric C. Harley ,  Anita Madan ,  Teresa L. Pinto

IPC: G01N23/20

CPC classification number: G01N23/20 ,  G01N2223/6116

Abstract: In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest.

Abstract translation: 在使用x射线衍射测量SOI衬底的顶部硅锗层上的应变的方法中，SOI衬底的上硅层的峰值衍射面积的位置是通过首先确定峰值衍射面积 在半导体晶片上形成的晶片内的参考焊盘（其中SOI厚度为约700-900埃）上硅层。 然后X射线束移动到要测量的感兴趣的焊盘上的该位置，并在感兴趣的焊盘上开始XRD扫描，以最终确定感兴趣焊盘的顶部硅锗层的应变。

公开(公告)号：US20100112762A1

公开(公告)日：2010-05-06

申请号：US12684551

申请日：2010-01-08

Applicant: Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

Inventor： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L29/66545 ,  H01L21/0237 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66553

Abstract: Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.

Abstract translation: 公开了制造具有设置在半导体结构的衬底的表面上的非外延薄膜的半导体结构的方法。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。

公开(公告)号：US20090173970A1

公开(公告)日：2009-07-09

申请号：US11969448

申请日：2008-01-04

Applicant: Thomas N. Adam ,  Rajendran Krishnasamy

Inventor： Thomas N. Adam ,  Rajendran Krishnasamy

IPC: H01L29/737 ,  H01L21/331

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/045

Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation in addition to silicon crystalline orientation to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation may be disposed on crystalline orientation . Alternatively, the region of silicon crystalline orientation may be disposed on crystalline orientation .

Abstract translation: 公开了一种制造异质结双极晶体管（HBT）的方法，其中HBT具有结合设置在包含硅晶取向<110>的衬底上的异质结双极结构的结构。 异质结双极结构可以包括发射极，基极和集电极。 衬底可以包括浅沟槽隔离（STI）区域和设置有集电极的深沟槽区域。 除了硅晶体取向<110>之外，衬底可以包括硅晶体取向<100>的区域，以通过使用混合取向技术（HOT）形成复合衬底。 结晶取向区域<100>可以设置在晶体取向110上。 或者，硅结晶取向区域<110>可以以结晶取向<100>设置。

公开(公告)号：US20090134460A1

公开(公告)日：2009-05-28

申请号：US12363239

申请日：2009-01-30

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC: H01L27/00 ,  H01L21/71

CPC classification number: H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract translation: 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US07485539B2

公开(公告)日：2009-02-03

申请号：US11332564

申请日：2006-01-13

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC: H01L21/76

CPC classification number: H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract translation: 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20080277690A1

公开(公告)日：2008-11-13

申请号：US12176624

申请日：2008-07-21

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC: H01L27/12

CPC classification number: H01L21/76259 ,  Y10S438/967

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract translation: 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。