公开(公告)号：US20240095180A1

公开(公告)日：2024-03-21

申请号：US18088170

申请日：2022-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Michael Estlick ,  Jay Fleischman ,  Michael J. Schulte ,  Bradford Beckmann ,  Yasuko Eckert

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1008

Abstract: The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240078197A1

公开(公告)日：2024-03-07

申请号：US18216098

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1642

Abstract: A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.

公开(公告)号：US11775799B2

公开(公告)日：2023-10-03

申请号：US16194958

申请日：2018-11-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Georgios Mappouras ,  Amin Farmahini-Farahani ,  Sudhanva Gurumurthi ,  Abhinav Vishnu ,  Gabriel H. Loh

IPC: G06N20/10 ,  G06N3/04 ,  G06F9/54 ,  G06F9/445 ,  G06N3/084

CPC classification number: G06N3/04 ,  G06F9/44505 ,  G06F9/544 ,  G06N3/084

Abstract: Systems, apparatuses, and methods for managing buffers in a neural network implementation with heterogeneous memory are disclosed. A system includes a neural network coupled to a first memory and a second memory. The first memory is a relatively low-capacity, high-bandwidth memory while the second memory is a relatively high-capacity, low-bandwidth memory. During a forward propagation pass of the neural network, a run-time manager monitors the usage of the buffers for the various layers of the neural network. During a backward propagation pass of the neural network, the run-time manager determines how to move the buffers between the first and second memories based on the monitored buffer usage during the forward propagation pass. As a result, the run-time manager is able to reduce memory access latency for the layers of the neural network during the backward propagation pass.

公开(公告)号：US20230207544A1

公开(公告)日：2023-06-29

申请号：US17560691

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

公开(公告)号：US11475305B2

公开(公告)日：2022-10-18

申请号：US15836080

申请日：2017-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06N3/04 ,  G06N3/08 ,  G06F3/0484 ,  G06K9/62 ,  G06N3/06 ,  G06F30/30 ,  G06V10/94

Abstract: An electronic device has an activation function functional block that implements an activation function. During operation, the activation function functional block receives an input including a plurality of bits representing a numerical value. The activation function functional block then determines a range from among a plurality of ranges into which the input falls, each range including a separate portion of possible numerical values of the input. The activation function functional block next generates a result of a linear function associated with the range. Generating the result includes using a separate linear function that is associated with each range in the plurality of ranges to approximate results of the activation function within that range.

公开(公告)号：US11342933B2

公开(公告)日：2022-05-24

申请号：US16220540

申请日：2018-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F17/00 ,  H03M7/30 ,  G06N20/00 ,  G06F17/18

Abstract: Described are systems and methods for lossy compression and restoration of data. The raw data is first truncated. Then the truncated data is compressed. The compressed truncated data can then be efficiently stored and/or transmitted using fewer bits. To restore the data, the compressed data is then decompressed and restoration bits are concatenated. The restoration bits are selected to compensate for statistical biasing introduced by the truncation.

公开(公告)号：US20220138107A1

公开(公告)日：2022-05-05

申请号：US17575991

申请日：2022-01-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F12/0877

Abstract: Systems, apparatuses, and methods for efficiently performing memory accesses in a computing system are disclosed. A computing system includes one or more clients, a communication fabric and a last-level cache implemented with low latency, high bandwidth memory. The cache controller for the last-level cache determines a range of addresses corresponding to a first region of system memory with a copy of data stored in a second region of the last-level cache. The cache controller sends a selected memory access request to system memory when the cache controller determines a request address of the memory access request is not within the range of addresses. The cache controller services the selected memory request by accessing data from the last-level cache when the cache controller determines the request address is within the range of addresses.

公开(公告)号：US11226900B2

公开(公告)日：2022-01-18

申请号：US16776416

申请日：2020-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Weon Taek Na ,  Yasuko Eckert ,  Mark H. Oskin ,  Gabriel H. Loh ,  William Louie Walker ,  Michael Warren Boyer

IPC: G06F12/0815 ,  G06F16/22 ,  G06F12/0831

Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.

公开(公告)号：US11106600B2

公开(公告)日：2021-08-31

申请号：US16256634

申请日：2019-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Paul Moyer

IPC: G06F12/10 ,  G06F12/126 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/1027

Abstract: A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.

公开(公告)号：US11018125B2

公开(公告)日：2021-05-25

申请号：US16927111

申请日：2020-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/433

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.