公开(公告)号：US12253961B2

公开(公告)日：2025-03-18

申请号：US16728114

申请日：2019-12-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Ravindra N. Bhargava ,  Guanhao Shen

IPC: G06F13/16 ,  G06F12/1009 ,  G11C8/12 ,  G11C11/406

Abstract: Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

公开(公告)号：US12158827B2

公开(公告)日：2024-12-03

申请号：US18091163

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20

Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.

公开(公告)号：US12038856B2

公开(公告)日：2024-07-16

申请号：US17961613

申请日：2022-10-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Brendan T. Mangan

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F13/1668 ,  G06F9/30043 ,  G06F12/0246 ,  G06F12/1009 ,  G06F13/1605

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US20240202289A1

公开(公告)日：2024-06-20

申请号：US18081540

申请日：2022-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： David Kaplan ,  Kedarnath Balakrishnan

IPC: G06F21/10 ,  G06F9/455

CPC classification number: G06F21/10 ,  G06F9/45558 ,  G06F2009/45587

Abstract: An electronic device includes a memory and controller circuitry. The controller circuitry, responsive to a read request to read encrypted data stored in the memory, acquires, from metadata stored with the encrypted data in the memory, an ownership identifier identifying a type of writing entity that stored the encrypted data in the memory. The controller circuitry uses the ownership identifier to control whether, when responding to the read request, data decrypted from the encrypted data is returned or substitute data is returned instead of data decrypted from the encrypted data.

公开(公告)号：US11704183B2

公开(公告)日：2023-07-18

申请号：US17544074

申请日：2021-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

CPC classification number: G06F11/0772 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/1004 ,  G06F11/1068 ,  H03M13/29

Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.

公开(公告)号：US11694739B2

公开(公告)日：2023-07-04

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

CPC classification number: G11C11/40615

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US20230004459A1

公开(公告)日：2023-01-05

申请号：US17864804

申请日：2022-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US20220091921A1

公开(公告)日：2022-03-24

申请号：US17544074

申请日：2021-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.

公开(公告)号：US20220028450A1

公开(公告)日：2022-01-27

申请号：US16938855

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C11/406 ,  G06F1/3203 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11200106B2

公开(公告)日：2021-12-14

申请号：US16705913

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  H03M13/29 ,  G06F11/10

Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.