公开(公告)号：US20180074824A1

公开(公告)日：2018-03-15

申请号：US15264002

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Eric Bainville ,  Jeffry E. Gonion ,  Gerard R. Williams, III ,  Andrew J. Beaumont-Smith

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30101 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893

Abstract: In an embodiment, an outer product engine is configured to perform outer product operations. The outer product engine may perform numerous multiplication operations in parallel on input vectors, in an embodiment, generating a resulting outer product matrix. In an embodiment, the outer product engine may be configured to accumulate results in a result matrix, performing fused multiply add (FMA) operations to produce the outer product elements (multiply) and to accumulate the outer product elements with previous elements from the result matrix memory (add). A processor may fetch outer product instructions, and may transmit the instructions to the outer product engine when the instructions become non-speculative in an embodiment. The processor may be configured to retire the outer product instructions responsive to transmitting them to the outer product engine.

公开(公告)号：US09852084B1

公开(公告)日：2017-12-26

申请号：US15017427

申请日：2016-02-05

Applicant: Apple Inc.

Inventor： Peter G. Soderquist ,  Pradeep Kanapathipillai ,  Bernard J. Semeria ,  Joshua P. de Cesare ,  David J. Williamson ,  Gerard R. Williams, III

IPC: G06F12/14 ,  G06F12/1009

CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F2212/1052

Abstract: Systems, apparatuses, and methods for modifying access permissions in a processor. A processor may include one or more permissions registers for managing access permissions. A first permissions register may be utilized to override access permissions embedded in the page table data. A plurality of bits from the page table data may be utilized as an index into the first permissions register for the current privilege level. An attribute field may be retrieved from the first permissions register to determine the access permissions for a given memory request. A second permissions register may also be utilized to set the upper and lower boundary of a region in physical memory where the kernel is allowed to execute. A lock register may prevent any changes from being made to the second permissions register after the second permissions register has been initially programmed.

公开(公告)号：US09582276B2

公开(公告)日：2017-02-28

申请号：US13629471

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F9/30087 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/522

Abstract: Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color.

Abstract translation: 在无序处理器管道中存在障碍的情况下执行存储器访问请求的顺序的方法和处理器。 在处理器管道的前端分配指令颜色，而指令操作仍然有序。 指令操作被放置在多个保留站中的任一个中，然后从保留站发出无序。 当在前端遇到屏障时，推测颜色发生变化，指令操作会被分配新的投机颜色。 核心接口单元维护建筑颜色，并且在屏障退出时改变架构颜色。 核心接口单元使用与建筑颜色匹配的推测颜色停止指令操作。

公开(公告)号：US09176879B2

公开(公告)日：2015-11-03

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US20150026413A1

公开(公告)日：2015-01-22

申请号：US13942780

申请日：2013-07-16

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III ,  Hari S. Kannan ,  Pavlos Konas

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026 ,  Y02D10/13

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides and/or irregular access patterns may be included in the matching patterns and may be detected for prefetch generation. In an embodiment, the AMPM prefetcher may implement a chained access map for large streaming prefetches. If a stream is detected, the AMPM prefetcher may allocate a pair of map entries for the stream and may reuse the pair for subsequent access map regions within the stream. In some embodiments, a quality factor may be associated with each access map and may control the rate of prefetch generation.

Abstract translation: 在一个实施例中，处理器可以实现基于访问映射模式匹配（AMPM）的预取器，其中模式可以包括一些高速缓存块的通配符。 通配符可以匹配对应的高速缓存块的任何访问（例如，无访问，请求访问，预取，成功预取等）。 此外，具有不规则步幅和/或不规则访问模式的模式可以被包括在匹配模式中，并且可以被检测用于预取生成。 在一个实施例中，AMPM预取器可以实现用于大型流预取的链接访问映射。 如果检测到流，则AMPM预取器可以为流分配一对映射条目，并且可以将该对重新使用在该流内的后续访问映射区域。 在一些实施例中，质量因子可以与每个访问映射关联，并且可以控制预取生成的速率。

公开(公告)号：US08775757B2

公开(公告)日：2014-07-08

申请号：US13626546

申请日：2012-09-25

Applicant: Apple Inc.

Inventor： R. Stephen Polzin ,  James B. Keller ,  Gerard R. Williams, III

IPC: G06F12/14

CPC classification number: G06F12/14 ,  G06F12/1441 ,  G06F21/575 ,  G06F21/74

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

公开(公告)号：US20140089589A1

公开(公告)日：2014-03-27

申请号：US13629471

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30087 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/522

Abstract: Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color.

Abstract translation: 在无序处理器管道中存在障碍的情况下执行存储器访问请求的顺序的方法和处理器。 在处理器管道的前端分配指令颜色，而指令操作仍然有序。 指令操作被放置在多个保留站中的任一个中，然后从保留站发出无序。 当在前端遇到屏障时，推测颜色发生变化，指令操作会被分配新的投机颜色。 核心接口单元维护建筑颜色，并且在屏障退出时改变架构颜色。 核心接口单元使用与建筑颜色匹配的推测颜色停止指令操作。