公开(公告)号：US20230056044A1

公开(公告)日：2023-02-23

申请号：US17821296

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  James Vash ,  Gaurav Garg ,  Sergio Kolor ,  Harshavardhan Kaushikkar ,  Ramesh B. Gunna ,  Steven R. Hutsell

IPC: G06F13/28 ,  G06F12/0815 ,  G06F12/109

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11537538B2

公开(公告)日：2022-12-27

申请号：US17242051

申请日：2021-04-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F11/34 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US11016913B1

公开(公告)日：2021-05-25

申请号：US16834148

申请日：2020-03-30

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US10802968B2

公开(公告)日：2020-10-13

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/0815 ,  G06F12/0813 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

公开(公告)号：US20200081840A1

公开(公告)日：2020-03-12

申请号：US16124713

申请日：2018-09-07

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang

IPC: G06F12/0855

Abstract: Systems, apparatuses, and methods for implementing coherence flows for dual-processing coherence and memory cache pipelines are disclosed. A dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. When a transaction is issued to the dual-processing pipeline, the coherence processing pipeline performs a duplicate tag lookup in parallel with the memory cache processing pipeline performing a memory cache tag lookup for the transaction. If the duplicate tag lookup is a hit, then the coherence processing pipeline locks the matching entry, the memory cache processing pipeline discards the original transaction, and a copyback request is sent to a coherent agent identified by the matching entry. When the copyback response is received by a communication fabric, the copyback response is issued to the memory cache processing pipeline. When the copyback response passes the global ordering point, the coherence processing pipeline clears the lock on the matching entry.

公开(公告)号：US20200081837A1

公开(公告)日：2020-03-12

申请号：US16125494

申请日：2018-09-07

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Sridhar Kotha ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang ,  Yu Zhang

IPC: G06F12/0815 ,  G06F12/0855

Abstract: Systems, apparatuses, and methods for implementing a distributed global ordering point are disclosed. A system includes at least a communication fabric, sequencing logic, and a plurality of coherence point pipelines. Each coherence point pipeline receives transactions from the communication fabric and then performs coherence operations and a memory cache lookup for the received transactions. The global ordering point of the system is distributed across the outputs of the separate coherence point pipelines. Device-ordered transactions travelling upstream toward memory are assigned sequence numbers by the sequencing logic. The transactions are speculatively issued from the communication fabric to the coherence point pipelines. Speculatively issuing the transactions to the coherence point pipelines may cause the transactions to pass through the distributed global ordering point out of order. Control logic on the downstream path reorders the transactions based on the assigned sequence numbers.

公开(公告)号：US10298511B2

公开(公告)日：2019-05-21

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04W72/12 ,  H04L12/863 ,  G06F13/16 ,  G06F9/54 ,  H04L12/865

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US10169235B2

公开(公告)日：2019-01-01

申请号：US14969360

申请日：2015-12-15

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Wolfgang H. Klingauf

IPC: G06F12/084 ,  G06F12/0815

Abstract: In an embodiment, an apparatus includes control circuitry and a memory configured to store a plurality of access instructions. The control circuitry is configured to determine an availability of a resource associated with a given access instruction of the plurality of access instructions. The associated resource is included in a plurality of resources. The control circuitry is also configured to determine a priority level of the given access instruction in response to a determination that the associated resource is unavailable. The control circuit is further configured to add the given access instruction to a subset of the plurality of access instructions in response to a determination that the priority level is greater than a respective priority level of each access instruction in the subset. The control circuit is also configured to remove the given access instruction from the subset in response to a determination that the associated resource is available.

公开(公告)号：US09990294B2

公开(公告)日：2018-06-05

申请号：US15052000

申请日：2016-02-24

Applicant: Apple Inc.

Inventor： Bikram Saha ,  Harshavardhan Kaushikkar ,  Sukalpa Biswas ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/0842

CPC classification number: G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

公开(公告)号：US20180063016A1

公开(公告)日：2018-03-01

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04L12/863

CPC classification number: H04L47/6295 ,  G06F9/546 ,  G06F13/1642 ,  H04L47/6275

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.