Abstract:
A system and device for driving high resolution monitors while reducing artifacts thereon. Utilization of Z-inversion polarity driving techniques to drive pixels in a display reduces power consumption of the display but tends to generate visible horizontal line artifacts caused by capacitances present between the pixels and data lines of the display. By introducing a physical shield between the pixel and data line elements, capacitance therebetween can be reduced, thus eliminating the cause of the horizontal line artifacts. The shield may be a common voltage line (Vcom) of the display.
Abstract:
A display may have thin-film transistor (TFT) circuitry on a substrate. An array of organic light-emitting diodes may be formed on the thin-film transistor circuitry. The display may include inorganic brittle layers and organic and metal layers that are ductile and mechanically robust. To help prevent propagation of cracks and other defects along the edge of the display, the display may be provided with crack stop structures and crack detection circuitry. The crack detection circuitry may include one or more loops that are formed along the periphery of the display. The crack stop structures may include TFT/OLED structures formed in a staggered configuration. At least some of the brittle layers can be removed from the panel edge. An additional adhesion layer may also be formed directly on the substrate to help prevent inorganic layers from debonding from the surface of the substrate.
Abstract:
A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode with an anode and cathode. The anodes may be formed from a patterned layer of metal. Thin-film transistor circuitry in the pixels may include transistors such as drive transistors and switching transistors. Data lines may supply data signals to the pixels and horizontal control lines may supply control signals to the gates of the transistors. A switching transistor may be coupled between a voltage initialization line and each anode. The voltage initialization lines and capacitor structures in the thin-film transistor circuitry may be formed using a layer of metal that is different than the layer of metal that forms the anodes.
Abstract:
An organic light-emitting diode display may have an array of pixel circuits. Each pixel circuit may contain an organic light-emitting diode that emits light, a drive transistor that controls current flow through the diode, and additional transistors such as switching transistors for loading data into the pixel circuit and emission transistors for enabling and disabling current flow through the drive transistor and diode. Gate driver circuitry may produce emission control signals that control the emission transistors. Display driver circuitry may generate a start signal with a digitally controlled pulse width. The start signal may be applied to shift register circuitry in the gate driver circuitry. The pulse width of the start signal may be adjusted to adjust the luminance of the display.
Abstract:
A display may have an array of pixels. Each pixel may have a light-emitting diode that emits light under control of a drive transistor. The organic light-emitting diodes may have a common cathode layer, a common electron layer, individual red, green, and blue emissive layers, a common hole layer, and individual anodes. The hole layer may have a hole injection layer stacked with a hole transport layer. Pixel circuits for controlling the diodes may be formed from a layer of thin-film transistor circuitry on a substrate. A planarization layer may cover the thin-film transistor layer. Lateral leakage current between adjacent diodes can be blocked by shorting the common hole layer to a metal line such as a bias electrode that is separate from the anodes. The metal line may be laterally interposed between adjacent pixels and may be formed on the planarization layer or embedded within the planarization layer.
Abstract:
An electronic device may have a flexible display with portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Signal lines may couple the display pixels to the contact pads. The signal lines may overlap the bend axis in the inactive area of the display. During fabrication, an etch stop may be formed on the display that overlaps the bend axis. The etch stop may prevent over etching of dielectric such as a buffer layer on a polymer flexible display substrate. A layer of polymer that serves as a neutral stress plane adjustment layer may be formed over the signal lines in the inactive area of the display. Upon bending, the neutral stress plane adjustment layer helps prevent stress in the signal lines.
Abstract:
Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.
Abstract:
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
Abstract:
A method is provided for fabricating an organic light emitting diode (OLED) display. The method includes forming a thin film transistor (TFT) substrate including a first metal layer and a second metal layer. The method also includes depositing a first passivation layer over the second metal layer, and forming a third metal layer over a channel region and a storage capacitor region. The third metal layer is configured to connect to a first portion of the second metal layer that is configured to connect to the first metal layer in a first through-hole through a gate insulator and the first passivation layer. The method further includes depositing a second passivation layer over the third metal layer, and forming an anode layer over the second passivation layer. The anode is configured to connect to a second portion of the third metal layer that is configured to connect to the second metal layer in a second through-hole of the first passivation layer and the second passivation layer.