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公开(公告)号：US20210295584A1
公开(公告)日：2021-09-23
申请号：US16825346
申请日：2020-03-20
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Klaeboe Langtind , Mark Underwood
Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.
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公开(公告)号：US11127187B2
公开(公告)日：2021-09-21
申请号：US16697984
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Ian Rudolf Bratt , Andreas Due Engh-Halstvedt , Alexander Eugene Chalfin , Andreas Loeve Selvik , Olof Henrik Uhrenholt , Thomas J. Olson
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions (40) for rendering, each region (40) comprising a respective area of the render output; and for sets of one or more primitives to be rendered, it is determined for which of the plurality of regions of the render output (40) the primitive(s) should be rendered; and for each region of the render output (40) it is determined the primitive(s) should be rendered for, geometry data for the primitive(s) is stored in memory in a respective data structure (42) along with an indication of state data that is to be used for rendering the primitive(s) for the region, such that the geometry data for the primitive(s) to be rendered is stored in a respective, different data structure (42) for each different region of the render output (40) it is determined the primitive(s) should be rendered for.
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公开(公告)号：US11036644B2
公开(公告)日：2021-06-15
申请号：US15423497
申请日：2017-02-02
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Edvard Fielding
IPC: G06F12/08 , G06F12/12 , G06F12/0897 , G06F12/0875 , G06F12/126 , G06F12/128
Abstract: When a data processing operation requires data that is stored in a first cache and the fetching of the data into the first cache is dependent upon data stored in another cache, and an attempt to read the data from the first cache “misses”, the data processing operation is added to a record of data processing operations that have missed in the first cache and the data that is required for the data processing operation is fetched into the first cache by reading the data that is required to fetch the data into the first cache from the another cache and then using that data from the another cache to fetch the required data into the first cache. When the data that is required for the data processing operation has been fetched into the first cache, the data processing operation is performed using the fetched data.
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公开(公告)号：US11036500B2
公开(公告)日：2021-06-15
申请号：US16661196
申请日：2019-10-23
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt
IPC: G06F9/30 , G06F9/38 , G06F12/0875 , G06F7/50
Abstract: Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AADDC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out. The atomic-add-with-carry instructions may be used within systems which accumulate a local sum value prior to a data value being returned into a local cache memory at which time the local sum value is added to the return data value. The atomic-add-with-carry instructions may also be used in embodiments comprising a coalescing tree of respective processing apparatus where the carry out values generated from local sums produced at each node are returned early to higher nodes within the hierarchy thereby releasing them to commence other processing.
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公开(公告)号：US20210158585A1
公开(公告)日：2021-05-27
申请号：US16698030
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Alexander Eugene Chalfin , Andreas Due Engh-Halstvedt , Olof Henrik Uhrenholt , Andreas Loeve Selvik
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. For each region of the render output it is determined a primitive should be rendered for, geometry data for the primitive is stored in memory in a respective data structure for the region in a compressed form, such that the geometry data for the primitive to be rendered is stored in a compressed form, in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.
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Patent Agency Ranking
公开(公告)号：US20210158584A1
公开(公告)日：2021-05-27
申请号：US16697903
申请日：2019-11-27
Applicant: Arm Limited
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Primitive data for rendering the primitive is then stored either in a combined data structure in memory that is associated with a plurality of different regions of the render output, or is stored in a respective data structure for each region of the render output it is determined the primitive should be rendered for. Which manner the primitive data is stored is determined in dependence on a property, e.g. a coverage, of the primitive.
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公开(公告)号：US10733782B2
公开(公告)日：2020-08-04
申请号：US16153359
申请日：2018-10-05
Applicant: Arm Limited
Inventor： Frode Heggelund , Andreas Due Engh-Halstvedt , Christian Vik Grovdal
Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
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公开(公告)号：US10706607B1
公开(公告)日：2020-07-07
申请号：US16280924
申请日：2019-02-20
Applicant: Arm Limited
Inventor： Peter William Harris , Edvard Fielding , Andreas Due Engh-Halstvedt , Lukasz Kulasza
Abstract: When a graphics texture mapping apparatus is to perform a texture filtering operation that uses the data values of a plurality of texels, the texture mapper first determines whether any of the data values of the texels to be used for the texture filtering operation are the same, and then selects a texture filtering operation to be performed using data values of the texels based on the determination. The texture mapper then performs the selected texture filtering operation using one or more of the data values of the texels to provide the required texture filtering operation output result.
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公开(公告)号：US20190108610A1
公开(公告)日：2019-04-11
申请号：US16153315
申请日：2018-10-05
Applicant: Arm Limited
Inventor： Lars Oskar Flordal , Toni Viki Brkic , Christian Vik Grovdal , Andreas Due Engh-Halstvedt , Frode Heggelund
CPC classification number: G06T1/60 , G06T1/20 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/405
Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
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公开(公告)号：US10255718B2
公开(公告)日：2019-04-09
申请号：US15393120
申请日：2016-12-28
Applicant: ARM Limited
Inventor： Frank Langtind , Andreas Due Engh-Halstvedt , Sandeep Kakarlapudi
Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.
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