公开(公告)号：US20240215332A1

公开(公告)日：2024-06-27

申请号：US17908224

申请日：2021-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Fengjuan LIU ,  Wei LIU ,  Tianmin ZHOU ,  Kun ZHAO

IPC: H10K59/124 ,  H10K39/34 ,  H10K59/12

CPC classification number: H10K59/124 ,  H10K39/34 ,  H10K59/1201

Abstract: The present disclosure provides a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a circuit layer disposed on a base substrate, an emitting structure layer and a photoelectric structure layer disposed on a side of the circuit layer away from the base substrate, the circuit layer includes at least one impurity absorption layer and at least one transistor, the transistor includes an active layer, and at least one insulation layer is provided between the impurity absorption layer and the active layer; an atomic ratio of a silicon element to a nitrogen element in the impurity absorption layer is 1:5 to 1:35.

公开(公告)号：US20230317826A1

公开(公告)日：2023-10-05

申请号：US18022620

申请日：2022-03-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Fengjuan LIU ,  Dongfang WANG ,  Wei LIU ,  Yuhang LU ,  Hongda SUN ,  Ce NING ,  Guangcai YUAN

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/40

CPC classification number: H01L29/66742 ,  H01L29/401 ,  H01L29/7869

Abstract: A method for manufacturing a thin film transistor, and a thin film transistor are provided. The method includes: forming an active layer on a substrate by a single patterning process; forming a gate insulating layer by deposition on a side of the active layer away from the substrate; forming a first via hole and a second via hole penetrating through the gate insulating layer by a single patterning process, the first and second via holes being located at two ends of the active layer respectively; and forming a first electrode, a gate electrode, and a second electrode on the gate insulating layer by a single patterning process, the first and second electrodes being connected to the active layer through the first and second via holes, respectively, and an orthographic projection of the gate electrode on the substrate at least partially overlapping that of the active layer on the substrate.

公开(公告)号：US20230163143A1

公开(公告)日：2023-05-25

申请号：US17919547

申请日：2021-11-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong WANG ,  Ce NING ,  Tianmin ZHOU ,  Wei YANG ,  Yunping DI ,  Rui HUANG ,  Binbin TONG ,  Liping LEI

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/1251 ,  H01L27/124 ,  G02F1/136295 ,  H01L27/1225 ,  G02F1/13685 ,  G02F1/136209

Abstract: An array substrate and a display panel, relating to the technical field of display. The array substrate includes a base substrate, and a thin film transistor group which is provided on one side of the base substrate and includes at least two thin film transistors, the thin film transistors being stacked in a direction perpendicular to the base substrate.

公开(公告)号：US20220223745A1

公开(公告)日：2022-07-14

申请号：US17761549

申请日：2021-05-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Jie HUANG ,  Nianqi YAO ,  Zhi WANG ,  Feng GUAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.

公开(公告)号：US20210225893A1

公开(公告)日：2021-07-22

申请号：US16765216

申请日：2019-12-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei YANG ,  Guangcai YUAN ,  Ce NING ,  Xinhong LU ,  Tianmin ZHOU ,  Xin YANG

IPC: H01L27/12

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

公开(公告)号：US20200286929A1

公开(公告)日：2020-09-10

申请号：US16318740

申请日：2018-04-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengliang LI ,  Ce NING ,  Song LIU ,  Wenlin ZHANG ,  Xuefei SUN

IPC: H01L27/12

Abstract: The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.

公开(公告)号：US20200066758A1

公开(公告)日：2020-02-27

申请号：US16531231

申请日：2019-08-05

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wei YANG ,  Guangcai YUAN ,  Ce NING ,  Xinhong LU

IPC: H01L27/12

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes: a base substrate; a first thin film transistor on one side of the base substrate, the first thin film transistor comprising: a first active layer, a first protection layer, a second protection layer, a first source and a first drain; wherein the first protection layer and the second protection layer are on one side of the first active layer away from the base substrate, and are separated from each other; the first protection layer and the second protection layer are configured to protect the first active layer from being etched during forming of a via-hole corresponding to the first source and/or a via-hole corresponding to the first drain,

公开(公告)号：US20160293628A1

公开(公告)日：2016-10-06

申请号：US14769422

申请日：2014-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce NING

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1333

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/136295 ,  G02F2201/121 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869

Abstract: The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of: forming patterns of a common electrode, a common electrode line, a gate line and a data line on a substrate by a single patterning process; forming an insulating layer; forming a pattern of an active layer by a single patterning process; forming a gate insulating layer and forming via-holes corresponding to the gate line, the data line and the active layer in the gate insulating layer by a single patterning process; and forming patterns of a pixel electrode, a gate electrode, a source electrode and a drain electrode by a single patterning process.

Abstract translation: 本公开提供一种薄膜晶体管（TFT）阵列基板，其制造方法和显示装置。 该方法包括以下步骤：通过单一图案化工艺在衬底上形成公共电极，公共电极线，栅极线和数据线的图案; 形成绝缘层; 通过单一图案化工艺形成有源层的图案; 形成栅极绝缘层，并通过单个图案化工艺在栅极绝缘层中形成对应于栅极线，数据线和有源层的通孔; 以及通过单一图案化工艺形成像素电极，栅电极，源电极和漏电极的图案。

公开(公告)号：US20240379631A1

公开(公告)日：2024-11-14

申请号：US18691021

申请日：2021-10-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Nianqi YAO ,  Jin YANG ,  Ce NING ,  Jiayu HE ,  Jie HUANG ,  Hehe HU ,  Kun ZHAO ,  Feifei LI ,  Zhengliang LI ,  Guangcai YUAN

IPC: H01L27/12 ,  H01L25/16 ,  H01L33/62

Abstract: A light-emitting substrate and a display device are disclosed, the light-emitting substrate includes: a base substrate including a light-emitting region; a plurality of first pads on a side of the base substrate and in the light-emitting region, where a material of the first pads includes Cu; and an oxidation protection layer on a side of the first pads away from the base substrate, where the plurality of first pads is used for bonding connection with a plurality of light-emitting units through the oxidation protection layer, a material of the oxidation protection layer includes CuNiX, and X includes one or any combination of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co or Sb.

公开(公告)号：US20240361628A1

公开(公告)日：2024-10-31

申请号：US18768052

申请日：2024-07-10

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangcai YUAN ,  Hehe HU ,  Changhan HSIEH ,  Shipei LI ,  Jiayu HE ,  Xin GU ,  Ce NING ,  Zhengliang LI

IPC: G02F1/133 ,  G02F1/1335 ,  G06F1/16 ,  H10K30/88

CPC classification number: G02F1/13318 ,  G02F1/133509 ,  G06F1/1652 ,  H10K30/88

Abstract: A photodetection backplane, a liquid crystal display panel and a liquid crystal display apparatus are provided. The photodetection backplane includes: a base substrate; a first organic switching unit arranged at a side of the base substrate; and an organic photodetector arranged at a same side of the base substrate as the first organic switching unit. The organic photodetector is electrically connected to the first organic switching unit, and at least one film layer of the organic photodetector and a film layer of the first organic switching unit are arranged in a same layer and made of a same material.
(FIG. 1)