公开(公告)号：US06563173B2

公开(公告)日：2003-05-13

申请号：US09859146

申请日：2001-05-16

申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

IPC分类号： H01L2900

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648

摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

公开(公告)号：US06541317B2

公开(公告)日：2003-04-01

申请号：US09848466

申请日：2001-05-03

申请人： K. Paul Muller ,  Dominic J. Schepis ,  Ghavam G. Shahidi

发明人： K. Paul Muller ,  Dominic J. Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L2100

CPC分类号： H01L29/66553 ,  H01L21/2257 ,  H01L21/7624 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66621

摘要： Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.

公开(公告)号：US06440807B1

公开(公告)日：2002-08-27

申请号：US09882095

申请日：2001-06-15

申请人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

发明人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

IPC分类号： H01L21336

CPC分类号： H01L29/7834 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66628 ,  Y10S438/976

摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

摘要翻译： 本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。 具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

公开(公告)号：US06387742B2

公开(公告)日：2002-05-14

申请号：US09862451

申请日：2001-05-23

申请人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/78648 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/763 ,  H01L23/3677 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

摘要翻译： 在选择的电子部件的制造期间，在基板上的选定位置处形成硅。 介电分离区形成在顶层硅层内，并填充有导热材料。 衬里材料可以在沉积导热材料之前任选地沉积。 在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

公开(公告)号：US06339005B1

公开(公告)日：2002-01-15

申请号：US09425394

申请日：1999-10-22

申请人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

发明人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

IPC分类号： H01L21336

CPC分类号： H01L29/66643 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/812

摘要： A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

摘要翻译： 公开了一种绝缘体上硅晶体管，其具有与身体的肖特基接触。 肖特基接触可以形成在栅极导体的源极和/或漏极侧。 在栅极导体的侧壁上形成有至少一部分是一次性的间隔物。 延伸区域设置在衬底下延伸在间隔物和栅极导体之下。 源极和漏极扩散区域被注入邻近延伸区域的衬底中。 然后移除间隔件的一次性部分以暴露延伸区域的一部分。 至少在延伸区域中形成金属层，导致肖特基接触。

公开(公告)号：US08389352B2

公开(公告)日：2013-03-05

申请号：US13025474

申请日：2011-02-11

申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

公开(公告)号：US08354314B2

公开(公告)日：2013-01-15

申请号：US13025474

申请日：2011-02-11

申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L21/8238

摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

公开(公告)号：US07955940B2

公开(公告)日：2011-06-07

申请号：US12551797

申请日：2009-09-01

申请人： Thomas Walter Dyer ,  Junedong Lee ,  Dominic J. Schepis

发明人： Thomas Walter Dyer ,  Junedong Lee ,  Dominic J. Schepis

IPC分类号： H01L21/331

CPC分类号： H01L21/185 ,  H01L21/265 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203

摘要： A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

摘要翻译： 形成SOI衬底的方法，SOI衬底中的二极管和SOI衬底中的电子器件以及使用SOI衬底形成的电子器件。 形成SOI衬底的方法包括在硅第一衬底上形成氧化物层; 将氢离子注入到氧化物层进入第一衬底中，以在衬底中形成断裂区; 在硅第二衬底上形成掺杂的电介质结合层; 将所述结合层的顶表面结合到所述氧化物层的顶表面; 通过沿着断裂区域热裂解第一基板来使第一基板变薄，以在氧化物层上形成硅层以形成键合的基片; 以及加热所述键合衬底以将掺杂剂从所述接合层驱动到所述第二衬底中，以在与所述接合层相邻的所述第二衬底中形成掺杂层。

公开(公告)号：US07781273B2

公开(公告)日：2010-08-24

申请号：US12127033

申请日：2008-05-27

申请人： Dominic J. Schepis ,  Huilong Zhu

发明人： Dominic J. Schepis ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

摘要翻译： 公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并具有不同高度的沟道区。 在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。 在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。 所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含 多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

公开(公告)号：US20100200937A1

公开(公告)日：2010-08-12

申请号：US12367759

申请日：2009-02-09

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L29/78 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。