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262 条记录 (耗时 0.028 秒)

    Scaler circuit
    61.
    发明授权
    Scaler circuit 失效
    整流电路

    公开(公告)号：US5604458A

    公开(公告)日：1997-02-18

    申请号：US457445

    申请日：1995-06-01

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/12 ,  G06J1/00 ,  H03G1/00 ,  G06F7/44

    CPC分类号： G06J1/00 ,  G06G7/12 ,  H03G1/0094

    摘要： A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.

    摘要翻译： 标量电路包括通过多条连接线彼此连接的串联逆变器。 多个输入线被提供给串联逆变器中的第一反相器的输入端。 在每个逆变器的输入和输出之间提供多条反馈线。 每个连接线，输入线和反馈线都提供电容和开关。 开关将电容的端子连接到地，同时断开该线的端部。 这些开关被协同地致动，使得反馈线和连接线中的有效复合电容基本相等。 此外，输入线和连接线中的复合电容基本相等。

    High-speed circuit for performing pattern matching of image data and the like suitable for large scale integration implementation
    62.
    发明授权
    High-speed circuit for performing pattern matching of image data and the like suitable for large scale integration implementation 失效
    用于执行适合于大规模集成实现的图像数据等的图案匹配的高速电路

    公开(公告)号：US5579411A

    公开(公告)日：1996-11-26

    申请号：US426587

    申请日：1995-04-21

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06T1/00 ,  G06F17/15 ,  G06K9/64 ,  G06T7/00 ,  G06K9/62

    CPC分类号： G06K9/6202 ,  G06F17/153

    摘要： A pattern matching system includes a circuit that matches an input image with a template based on a correlation function. The circuit has a structure which makes it particularly suitable for implementation in Large Scale Integration (LSI) technologies. A pattern matching circuit according to this invention sets up a threshold value of a correlation coefficient and evaluates the following formula,E=N.sup.2 {.SIGMA.(f.sub.i -f.sub.m) (g.sub.i -g.sub.m)}.sup.2 -p.sub.th.sup.2 N.sup.2 .sigma..sub.f.sup.2 .sigma..sub.g.sup.2where N is a number of input data points. f.sub.1 is an input data point. f.sub.m is a mean value of input data points. g.sub.1 is a template data point. g.sub.m is a mean value of template data points. .sigma..sub.f is a standard deviation of input data points and .sigma..sub.g is a standard deviation of template data points in a range over a threshold value.

    摘要翻译： 模式匹配系统包括基于相关函数将输入图像与模板匹配的电路。 该电路具有特别适用于大规模集成（LSI）技术实现的结构。 根据本发明的模式匹配电路建立相关系数的阈值，并且评估下列公式：E = N2 {SIGMA（fi-fm）（gi-gm）} 2-pth2N2 sigma f2 sigma g2其中N是 输入数据点数。 f1是输入数据点。 fm是输入数据点的平均值。 g1是模板数据点。 gm是模板数据点的平均值。 西格玛f是输入数据点的标准偏差，σg是在超过阈值的范围内的模板数据点的标准偏差。

    Method of multiplying an analog value by a digital value
    63.
    发明授权
    Method of multiplying an analog value by a digital value 失效
    将模拟值乘以数字值的方法

    公开(公告)号：US5490099A

    公开(公告)日：1996-02-06

    申请号：US304475

    申请日：1994-09-12

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/16 ,  G06J1/00 ,  H03M1/80

    CPC分类号： G06J1/00 ,  H03M1/804

    摘要： A method for directly multiplying an analog and a digital data without converting from analog-to-digital or digital-to-analog. An analog input voltage is provided to a plurality of switches. A digital input voltage including bits b.sub.0 to b.sub.7 which are provided as control signals to the switches. The switch output is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.

    摘要翻译： 一种用于直接将模拟和数字数字相乘而不从模数转换为数模或数模转换的方法。 模拟输入电压被提供给多个开关。 包括作为开关的控制信号提供的位b0至b7的数字输入电压。 开关输出通过电容耦合进行积分给出权重，并且通过具有数字输入的最高有效位（“MSB”）的双重权重的电容耦合CP添加符号位。

    Incrementing and decrementing counter circuits
    65.
    发明授权
    Incrementing and decrementing counter circuits 失效
    递增递减计数器电路

    公开(公告)号：US5467376A

    公开(公告)日：1995-11-14

    申请号：US308460

    申请日：1994-09-19

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06F7/50 ,  G06F7/505 ,  H03K25/00

    CPC分类号： G06F7/5055

    摘要： A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.

    摘要翻译： 计数器电路将完全计数转换为零计数，将零计数转换为完全计数。 根据本发明的递增计数器电路具有多个具有逐步阈值的阈值电路。 最高阈值电路的输出用作其他阈值电路的截止信号。 根据本发明的递减计数器电路具有从最低阈值到最高阈值的多个阈值电路。 最低阈值电路的输出用作其他阈值电路的闭合信号。

    Digital-to-analog converter employing a common trigger and reference signal
    66.
    发明授权
    Digital-to-analog converter employing a common trigger and reference signal 失效
    采用公共触发和参考信号的数模转换器

    公开(公告)号：US5455581A

    公开(公告)日：1995-10-03

    申请号：US154519

    申请日：1993-11-19

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： H03M1/84 ,  H03M1/82

    CPC分类号： H03M1/82

    摘要： The D/A converter comprises: a digital counter receiving a reference clock pluses and a reference voltage as a start signal so as to output a stop signal when the digital counter counts the reference clock pulses until a predetermined number; and a number is reached, and an RC circuit having a resister and a capacitor receiving the reference voltage so as to be charged by a predetermined time constant until the stop signal is inputted to the RC circuit, whereby the RC circuit is charged up to a voltage corresponding to a time distance between the start signal and the stop signal.

    摘要翻译： D / A转换器包括：数字计数器接收参考时钟脉冲和参考电压作为起始信号，以便当数字计数器对参考时钟脉冲进行计数直到预定数量时输出停止信号; 并且到达一个数字，以及RC电路，具有接收参考电压的电阻和电容器，以便以预定的时间常数充电直到停止信号被输入到RC电路，由此将RC电路充电到 对应于起始信号和停止信号之间的时间距离的电压。

    Multiplication circuit for multiplying analog inputs by digital inputs
    69.
    发明授权
    Multiplication circuit for multiplying analog inputs by digital inputs 失效
    乘法电路，用于通过数字输入将模拟输入相乘

    公开(公告)号：US5396442A

    公开(公告)日：1995-03-07

    申请号：US137738

    申请日：1993-10-19

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06J1/00 ,  H03M1/80

    CPC分类号： G06J1/00 ,  H03M1/804

    摘要： A multiplication circuit for multiplying an analog input by a digital input. The digital input has a plurality of bits. The circuit has a circuit input terminal for receiving the analog input and a circuit output terminal for outputting the results of multiplication of the analog input by the digital input. The circuit also has a plurality of capacitances and a plurality of switching devices.

    摘要翻译： 乘法电路，用于将模拟输入乘以数字输入。 数字输入具有多个位。 电路具有用于接收模拟输入的电路输入端子和用于输出通过数字输入的模拟输入相乘结果的电路输出端子。 该电路还具有多个电容和多个开关装置。

    Absolute value circuit
    70.
    发明授权
    Absolute value circuit 失效
    绝对值电路

    公开(公告)号：US5394107A

    公开(公告)日：1995-02-28

    申请号：US111870

    申请日：1993-08-26

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G01R19/22 ,  G06G7/25 ,  H03K5/00

    CPC分类号： G01R19/22 ,  G06G7/25

    摘要： An absolute value circuit for analog type processing combines an analog inverter circuit and a maximum circuit. The inverter circuit uses an operational amplifier comprised of CMOS inverters which are connected in a cascade with a gain of 1. The maximum circuit includes a pair of nMOS transistors, the source follower outputs of which are connected to a common output.

    摘要翻译： 用于模拟型处理的绝对值电路组合了模拟逆变器电路和最大电路。 逆变器电路使用由CMOS反相器组成的运算放大器，其以1的增益级联连接。最大电路包括一对nMOS晶体管，其源极跟随器输出端连接到公共输出端。