公开(公告)号：US20120044004A1

公开(公告)日：2012-02-23

申请号：US12857674

申请日：2010-08-17

申请人： Robert F. Payne ,  Marco Corsi

发明人： Robert F. Payne ,  Marco Corsi

IPC分类号： H03L7/00

CPC分类号： H03M1/08 ,  H03M1/1215

摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

摘要翻译： 到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。 然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。 即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。 这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配 带宽。

公开(公告)号：US20110018750A1

公开(公告)日：2011-01-27

申请号：US12896603

申请日：2010-10-01

申请人： Robert F. Payne ,  Marco Corsi

发明人： Robert F. Payne ,  Marco Corsi

IPC分类号： H03M1/06 ,  H03L7/06 ,  H03M1/66

CPC分类号： G05F3/265

摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.

摘要翻译： 提供开关电流源。 开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。 与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。 然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

公开(公告)号：US07863985B1

公开(公告)日：2011-01-04

申请号：US12511768

申请日：2009-07-29

申请人： Marco Corsi ,  Kenneth G. Maclean

发明人： Marco Corsi ,  Kenneth G. Maclean

IPC分类号： H03F1/14

CPC分类号： H03F1/32 ,  H03F1/14 ,  H03F3/19 ,  H03F2200/72 ,  H03F2200/91

摘要： An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.

摘要翻译： 提供放大器的输出级。 放大器通常提供对公共基极（或栅极）放大器晶体管的基极 - 集电极（或栅极 - 漏极）电容产生的误差电流的补偿。 该阶段通过利用三晶体威尔逊电流镜将误差电流与镜像偏置电流组合以减少公共基极（或栅极）放大器晶体管上的负载电流来实现。

公开(公告)号：US07782096B2

公开(公告)日：2010-08-24

申请号：US11876943

申请日：2007-10-23

申请人： Marco Corsi ,  Robert Payne

发明人： Marco Corsi ,  Robert Payne

IPC分类号： H03K5/00

CPC分类号： G11C27/026 ,  H03M1/0624 ,  H03M1/1245

摘要： A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant. A second capacitor is provided, having a first terminal connected to the first terminal of the resistor and having a second terminal connected to a power supply terminal. The second capacitor substantially reduces frequency-dependent harmonic distortion.

摘要翻译： 跟踪和保持电路，其能够跟踪模拟输入信号，并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。 提供了第一电容器，其具有连接到电源端子的第一端子。 当处于导通状态时，跟踪电路通过将跟踪电压施加到电阻器的第一端，通过电阻器向第一电容器的与模拟输入信号的电压相对应的第二端施加跟踪电压，第二 电阻器的端子连接到第一电容器的第二端子。 响应于轨道信号和保持信号的开关操作以响应于轨道信号将跟踪电路切换到接通状态，并且响应于保持信号而将其切换到关闭状态，从轨道信号变为时间 保持信号包括采样时刻。 提供了第二电容器，其具有连接到电阻器的第一端子的第一端子，并且具有连接到电源端子的第二端子。 第二电容器大大降低了频率相关的谐波失真。

公开(公告)号：US07636875B2

公开(公告)日：2009-12-22

申请号：US11697041

申请日：2007-04-05

申请人： Marco Corsi ,  Robert Floyd Payne

发明人： Marco Corsi ,  Robert Floyd Payne

IPC分类号： G06F11/00

CPC分类号： H03M9/00 ,  H04L25/14

摘要： A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

摘要翻译： 数字数据接口系统包括被配置为在多条数据线上传输数据字的数据发送器。 数据字可以包括具有从最低位数到最高位数的位数顺序的多个数字数据位，具有较高噪声含量的最低有序位数和具有较高谐波含量的最高有序位数。 该系统还包括编码器，其被配置为将多个数字数据位排列为串行化数据集，以由数据发送器在多个数据线中的每一条数据线上发送，其中至少一个串行化数据组的连续数据位被匹配，使得位 其中较高谐波含量与较高噪声含量的比特匹配，以便基本上减轻数据字的噪声内容和谐波内容中的至少一个。

公开(公告)号：US20090219059A1

公开(公告)日：2009-09-03

申请号：US12393164

申请日：2009-02-26

申请人： Marco Corsi ,  Robert F. Payne

发明人： Marco Corsi ,  Robert F. Payne

IPC分类号： G11C27/02

CPC分类号： G11C27/026 ,  H03M1/0624 ,  H03M1/1245

摘要： A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant.

摘要翻译： 提供跟踪和保持电路。 该跟踪和保持电路适于跟踪模拟输入信号并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。 优选地，跟踪和保持电路包括双向电流源，其通过第一输出节点和第二输出节点来源和吸收电流，单位增益放大器耦合到双向的第一和第二输出节点 电流源，并且接收模拟输入信号，耦合到单位增益放大器的输出的电阻器和耦合在电阻器和地之间的电容器。 然而，感兴趣的是双向电流源，其包括适于接收轨道信号和保持信号并且耦合到第一和第二输出节点的差分输入电路以及耦合到 差分输入电路。 RC网络接收模拟输入信号，并被缩放以改变零点的位置以减小采样时刻的信号依赖性。

公开(公告)号：US07327166B2

公开(公告)日：2008-02-05

申请号：US11206406

申请日：2005-08-18

申请人： Alfio Zanchi ,  Marco Corsi

发明人： Alfio Zanchi ,  Marco Corsi

IPC分类号： H03K19/0175 ,  G05F1/10

CPC分类号： G05F3/222 ,  H03F1/26 ,  H03F1/34 ,  H03F3/005 ,  H03F3/45475 ,  H03F2200/372 ,  H03F2200/453 ,  H03F2203/45134 ,  H03F2203/45136 ,  H03F2203/45512 ,  H03F2203/45628 ,  H03F2203/45722

摘要： A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on the voltage reference lines. The reference voltage circuit may be adapted for a switched capacitor ADC.

摘要翻译： 具有由包含在闭环中的匹配缓冲器驱动的开环缓冲器的参考电压电路产生稳定的差分或单端电压，同时最小化信号相关的短期和长期漂移。 开环缓冲器可以是闭环缓冲器的复制品，减少耦合在电压参考线上的信号的影响。 参考电压电路可以适用于开关电容器ADC。

公开(公告)号：US20070075689A1

公开(公告)日：2007-04-05

申请号：US11242504

申请日：2005-10-03

申请人： Russell Kinder ,  Marco Corsi

发明人： Russell Kinder ,  Marco Corsi

IPC分类号： G05F1/24

CPC分类号： H02M3/1582 ,  H02M2001/009

摘要： A dual output buck-boost power converter operates with a single inductor to achieve high efficiency with automatic or inherent load balancing. Switches associated with the opposite polarity outputs are driven based on feedback signals, with one feedback signal being a reference voltage and another feedback signal being related to an opposite polarity output. The opposite polarity feedback signal is provided to a comparator with a reversed polarity to achieve a simple balanced control that maintains polarity outputs. The power converter delivers power to each output with each switching cycle and uses a single inductor to achieve high efficiency performance.

摘要翻译： 双输出降压 - 升压功率转换器采用单个电感器工作，通过自动或固有的负载平衡实现高效率。 与相反极性输出相关联的开关基于反馈信号被驱动，一个反馈信号是参考电压，另一个反馈信号与相反的极性输出相关。 反相极性反馈信号提供给具有相反极性的比较器，以实现维持极性输出的简单平衡控制。 电源转换器在每个开关周期向每个输出提供电源，并使用单个电感器实现高效率性能。

公开(公告)号：US06630866B2

公开(公告)日：2003-10-07

申请号：US10005463

申请日：2001-12-03

申请人： Neil Gibson ,  Marco Corsi ,  Tobin Hagan

发明人： Neil Gibson ,  Marco Corsi ,  Tobin Hagan

IPC分类号： H03F326

CPC分类号： H03F3/26 ,  H03F3/3072 ,  H03F2203/30078 ,  H03F2203/30111

摘要： The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

摘要翻译： 本发明提供一种高β运算放大器输出级（100）。 运算放大器输出级与所公开的常规方法的优点高达beta2而不是单个beta。 本发明使用具有多个跨线回路的预驱动器子级（122）来实现这一点，使得没有到最终子级（123）的净信号损耗。 所公开的运算放大器输出级的输出采用以下形式：当与局部反馈电路一起使用时，速度性能增加并且带宽被扩展。

公开(公告)号：US06249184B1

公开(公告)日：2001-06-19

申请号：US09452029

申请日：1999-11-30

申请人： Marco Corsi

发明人： Marco Corsi

IPC分类号： H03F345

CPC分类号： H03F3/4517 ,  H03F3/45094 ,  H03F3/45587 ,  H03F2203/45406 ,  H03F2203/45424 ,  H03F2203/45431

摘要： A rail-to-rail input stage (20) for an operational amplifier having a constant transconductance (Gm) over a common mode range. The input stage has a cross-coupled quad circuit (Q9, Q10, Q15, Q16) having an essentially infinite transconductance, and pair of transistors (Q5, 6) running at the same current as input transistors (Q1, Q2) when active, whereby the pair of transistors (Q5, Q6) establish a constant transconductance of the input stage (20).

摘要翻译： 一种用于在共模范围内具有恒定跨导（Gm）的运算放大器的轨到轨输入级（20）。 输入级具有具有基本上无限跨导的交叉耦合四电路（Q9，Q10，Q15，Q16）以及当与有源时在与输入晶体管（Q1，Q2）相同的电流下运行的一对晶体管（Q5,6） 由此一对晶体管（Q5，Q6）建立输入级（20）的恒定跨导。