公开(公告)号：US20150137232A1

公开(公告)日：2015-05-21

申请号：US14510600

申请日：2014-10-09

申请人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao ,  Hung-Der Su ,  Kuo-Cheng Chang

发明人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao ,  Hung-Der Su ,  Kuo-Cheng Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L29/66681 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/6681 ,  H01L29/7816

摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件包括：漂移区，隔离氧化区，第一氧化物区，第二氧化物区，栅极，体区，源极和漏极。 隔离氧化物区域，第一氧化物区域和第二氧化物区域分别具有隔离厚度，第一厚度和第二厚度，其中第二厚度小于第一厚度。 本发明可以降低导通电阻而不降低第一氧化区和第二氧化区的LDMOS器件的击穿电压。

公开(公告)号：US20150028417A1

公开(公告)日：2015-01-29

申请号：US14483520

申请日：2014-09-11

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/0878 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。 高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。 从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

公开(公告)号：US20150021615A1

公开(公告)日：2015-01-22

申请号：US14040670

申请日：2013-09-28

申请人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

发明人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

IPC分类号： H01L29/872 ,  H01L29/66 ,  H01L29/868

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66212

摘要： The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

摘要翻译： 本发明公开了一种接合势垒肖特基（JBS）二极管及其制造方法。 JBS二极管包括：N型氮化镓（GaN）衬底; 形成在N型GaN衬底上的氮化镓铝（AlGaN）阻挡层; 在N型GaN衬底上形成的P型氮化镓（GaN）层; 至少部分地形成在AlGaN阻挡层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN阻挡层之间形成肖特基接触; 以及阴极导电层，其形成在N型GaN衬底上，其中在阴极导电层和N型GaN衬底之间形成欧姆接触，并且阴极导电层不直接连接到阳极导电层 。

公开(公告)号：US20140377940A1

公开(公告)日：2014-12-25

申请号：US14482858

申请日：2014-09-10

申请人： Tsung-Yi Huang ,  Jin-Lian Su

发明人： Tsung-Yi Huang ,  Jin-Lian Su

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L29/66136 ,  H01L21/265 ,  H01L21/76224 ,  H01L27/0255 ,  H01L27/0814 ,  H01L29/0649

摘要： The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.

摘要翻译： 本发明公开了一种瞬态电压抑制器（TVS）电路及其二极管装置及其制造方法。 TVS电路用于耦合到受保护电路以限制输入到保护电路的瞬态电压的幅度。 TVS电路包括抑制器装置和至少二极管装置。 二极管器件形成在衬底中，其包括：在衬底中形成的阱; 形成在所述上表面下方的分离区域; 阳极区域和阴极区域，分别形成在上表面下方的分离区域的两侧，其中阳极区域和阴极区域被分离区域分离; 以及掩埋层，其形成在阱下方的衬底中，具有较高的杂质密度和与该阱相同的导电类型。

公开(公告)号：US20140179079A1

公开(公告)日：2014-06-26

申请号：US14044626

申请日：2013-10-02

申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC分类号： H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a manufacturing method of a lateral double diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes: a substrate, an epitaxial layer, a first conductivity type channel stop region, a first conductivity type top region, an isolation oxide region, a field oxide region, a first conductivity type well, a gate, a second conductivity type lightly doped region, a second conductivity type source, and a second conductivity type drain. The present invention defines the channel stop region, the top region, the isolation oxide region, and the field oxide region by a same oxide region mask, wherein the isolation oxide region and the field oxide region are located on the channel stop region and the top region respectively.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件的制造方法。 LDMOS器件包括：衬底，外延层，第一导电类型沟道阻挡区，第一导电类型顶区，隔离氧化物区，场氧化物区，第一导电型阱，栅极，第二导电类型 轻掺杂区域，第二导电型源极和第二导电类型漏极。 本发明通过相同的氧化物区掩模限定了通道阻挡区域，顶部区域，隔离氧化物区域和场氧化物区域，其中隔离氧化物区域和场氧化物区域位于通道停止区域和顶部 区域。

公开(公告)号：US08759913B2

公开(公告)日：2014-06-24

申请号：US13472344

申请日：2012-05-15

申请人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao

发明人： Tsung-Yi Huang ,  Ching-Yao Yang ,  Wen-Yi Liao

IPC分类号： H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/66659

摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes: a drift region, a gate, a source, a drain, a dielectric layer, and a conductive layer. The drift region includes a first region and a second region. The gate is formed on the substrate, and overlaps the first region from top view. The source and drain are formed at both sides of the gate respectively, and the drain is located in the second region. The drain and the gate are separated by a portion of the second region from top view. The dielectric layer is formed by dielectric material on the gate and the second region. The conductive layer is formed by conductive material on the dielectric layer, and overlaps at least part of the second region from top view.

摘要翻译： 本发明公开了一种双扩散漏极金属氧化物半导体（DDMOS）器件及其制造方法。 DDDMOS器件形成在衬底中，并且包括：漂移区，栅极，源极，漏极，电介质层和导电层。 漂移区域包括第一区域和第二区域。 栅极形成在衬底上，并且从顶视图与第一区域重叠。 源极和漏极分别形成在栅极的两侧，漏极位于第二区域中。 漏极和栅极由顶视图的第二区域的一部分分开。 电介质层由栅极和第二区域上的电介质材料形成。 导电层由电介质层上的导电材料形成，并从顶视图与第二区域的至少一部分重叠。

公开(公告)号：US08754476B2

公开(公告)日：2014-06-17

申请号：US13185951

申请日：2011-07-19

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在衬底的阱中。 高电压装置包括：场氧化物区域; 栅极，其形成在基板的表面上，栅极的一部分位于场氧化物区域的上方; 源极和漏极，分别形成在栅极的两侧; 以及第一低浓度掺杂区，其形成在栅极下方并且具有低于所围绕的阱的杂质浓度，其中从顶视图来看，第一低浓度掺杂区具有栅极内的面积并且不大于 栅极的面积，第一低浓度掺杂区域的深度比源极和漏极深。

公开(公告)号：US08728895B1

公开(公告)日：2014-05-20

申请号：US14146528

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/336

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。 为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

公开(公告)号：US20140120679A1

公开(公告)日：2014-05-01

申请号：US14146528

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/28 ,  H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。 为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

公开(公告)号：US08685824B2

公开(公告)日：2014-04-01

申请号：US13529963

申请日：2012-06-21

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7817 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

摘要翻译： 本发明公开了一种混合式高压装置及其制造方法。 混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接 在宽度方向上以交替的顺序布置。 此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。