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    Method and apparatus for securing programming data of a programmable logic device
    64.
    发明授权
    Method and apparatus for securing programming data of a programmable logic device 失效
    用于保护可编程逻辑器件的编程数据的方法和装置

    公开(公告)号：US5768372A

    公开(公告)日：1998-06-16

    申请号：US617664

    申请日：1996-03-13

    申请人： Chiakang Sung ,  Bonnie I. Wang

    发明人： Chiakang Sung ,  Bonnie I. Wang

    IPC分类号： G06F1/00 ,  G06F21/00 ,  H03K19/177 ,  H04L9/00 ,  H03K19/007

    CPC分类号： H03K19/17768 ,  G06F21/6209 ,  G06F21/79 ,  G06F2221/2107 ,  G06F2221/2113

    摘要： An SRAM-based programmable logic device having decompression and decryption circuits between its EPROM nonvolatile programming data storage and its SRAM programming registers is secured against copying of the programming data because a would-be copyist would need to know the compression and encryption used. In a system and method for programming the device, a user station preferably contains a plurality of possible encryptions and a plurality of possible compression schemes. An encryption and compression scheme are selected, preferably at random, by the user or by the programming software in the user station. Data indicating which encryption and compression scheme were chosen are included in the programming data to allow decompression and decryption.

    摘要翻译： 在其EPROM非易失性编程数据存储器及其SRAM编程寄存器之间具有解压缩和解密电路的基于SRAM的可编程逻辑器件被保护以防止编程数据的复制，因为将要存档的抄写员将需要知道使用的压缩和加密。 在用于对该设备进行编程的系统和方法中，用户站优选地包含多个可能的加密和多个可能的压缩方案。 优选地由用户或用户站中的编程软件随机地选择加密和压缩方案。 指示哪个加密和压缩方案被选择的数据被包括在编程数据中以允许解压缩和解密。

    Write-leveling implementation in programmable logic devices
    65.
    发明授权
    Write-leveling implementation in programmable logic devices 有权
    在可编程逻辑器件中编写调平实现

    公开(公告)号：US08671303B2

    公开(公告)日：2014-03-11

    申请号：US13349228

    申请日：2012-01-12

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    67.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20120106264A1

    公开(公告)日：2012-05-03

    申请号：US13349228

    申请日：2012-01-12

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G11C7/10 ,  H03L7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Write-leveling implementation in programmable logic devices
    68.
    发明授权
    Write-leveling implementation in programmable logic devices 有权
    在可编程逻辑器件中编写调平实现

    公开(公告)号：US08122275B2

    公开(公告)日：2012-02-21

    申请号：US11843123

    申请日：2007-08-22

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    Multiple data rate interface architecture
    69.
    发明授权
    Multiple data rate interface architecture 失效
    多数据速率接口架构

    公开(公告)号：US06946872B1

    公开(公告)日：2005-09-20

    申请号：US10623394

    申请日：2003-07-18

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    PCI-compatible programmable logic devices
    70.
    发明授权
    PCI-compatible programmable logic devices 有权
    PCI兼容的可编程逻辑器件

    公开(公告)号：US06646467B1

    公开(公告)日：2003-11-11

    申请号：US10147200

    申请日：2002-05-17

    申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pendersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

    摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 设备上的一些寄存器紧密耦合，用于数据输入和输出到器件的数据信号输入/输出引脚。 至少这些寄存器的时钟信号输入端也紧密耦合到器件的时钟信号输入引脚。 在数据信号输入/输出引脚和上述寄存器的数据输入端之间提供可编程输入延迟，以帮助补偿器件上的时钟信号偏移。