公开(公告)号：US20090059668A1

公开(公告)日：2009-03-05

申请号：US11892979

申请日：2007-08-29

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0491

摘要： A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.

公开(公告)号：US07499335B2

公开(公告)日：2009-03-03

申请号：US11703916

申请日：2007-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/107 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

摘要翻译： 在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。 至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。 擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。 这可以避免热空穴注入引起的室温漂移和电荷损失。

公开(公告)号：US20080005434A1

公开(公告)日：2008-01-03

申请号：US11748984

申请日：2007-05-15

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yu-Lan Kuo

IPC分类号： G06F13/00

CPC分类号： G06F13/4291

摘要： Various embodiments increase the speed of communication over a multi-mode bus by communicating data over multiple pins in the same direction. The bus includes multiple data communication pins communicating over the bus. The bus includes a chip select pin indicating whether communication is occurring between the integrated circuit and another integrated circuit. The bus includes a clock pin. The bus includes a mode control circuit. In one mode, two of the data communication pins communicate in opposite directions between the integrated circuit and another integrated circuit. In another mode, two of the data communication pins communicate in a same direction between the integrated circuit and another integrated circuit. In some embodiments, the bus follows a Serial Peripheral Interface standard. In various embodiments, data is communicated from the integrated circuit to another integrated circuit, or from another integrated circuit to the integrated circuit.

摘要翻译： 各种实施例通过在相同方向上在多个引脚上传送数据来增加多模总线上的通信速度。 总线包括通过总线通信的多个数据通信引脚。 总线包括芯片选择引脚，指示集成电路和另一集成电路之间是否发生通信。 总线包括一个时钟引脚。 总线包括模式控制电路。 在一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间的相反方向上通信。 在另一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间沿相同的方向通信。 在一些实施例中，总线遵循串行外设接口标准。 在各种实施例中，数据从集成电路传送到另一集成电路，或从另一集成电路传送到集成电路。

公开(公告)号：US06219290B1

公开(公告)日：2001-04-17

申请号：US09172274

申请日：1998-10-14

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/28

摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

摘要翻译： 描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。 在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如 由参考单元电路路径建立在感测电路比较器的参考输入端上。 一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

公开(公告)号：US5818764A

公开(公告)日：1998-10-06

申请号：US796821

申请日：1997-02-06

申请人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

发明人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16 ,  G11C16/00

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16

摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

摘要翻译： 提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。 该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。 块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。 因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

公开(公告)号：US08891312B2

公开(公告)日：2014-11-18

申请号：US13453312

申请日：2012-04-23

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

摘要翻译： 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US08723559B2

公开(公告)日：2014-05-13

申请号：US13603815

申请日：2012-09-05

申请人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

摘要翻译： 可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。 向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流 源电压，克服第一静电流。 此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压 。

公开(公告)号：US20140062543A1

公开(公告)日：2014-03-06

申请号：US13603815

申请日：2012-09-05

申请人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03K3/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

摘要翻译： 可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。 向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流 源电压，克服第一静电流。 此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压 。

公开(公告)号：US20140028367A1

公开(公告)日：2014-01-30

申请号：US13556579

申请日：2012-07-24

申请人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H03K5/06

CPC分类号： H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

摘要翻译： 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟 输出缓冲区延迟。

公开(公告)号：US08638636B2

公开(公告)日：2014-01-28

申请号：US12816960

申请日：2010-06-16

申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C8/00

CPC分类号： G11C16/16

摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。