公开(公告)号：US06219290B1

公开(公告)日：2001-04-17

申请号：US09172274

申请日：1998-10-14

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  I-Long Lee ,  Yin-Shang Liu ,  Ray-Lin Wan

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/28

摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.

摘要翻译： 描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。 在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如 由参考单元电路路径建立在感测电路比较器的参考输入端上。 一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

公开(公告)号：US06255900B1

公开(公告)日：2001-07-03

申请号：US09284435

申请日：1999-04-12

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Ken-Hui Chen ,  Tien-Shin Ho ,  I-Long Lee ,  Tzeng-Hei Shiau ,  Ray-Lin Wan

IPC分类号： G05F110

CPC分类号： G11C16/30 ,  G05F3/242 ,  G11C5/145 ,  G11C16/08 ,  H02M3/07

摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.

摘要翻译： 提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。 电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。 升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值 升压速率直到第二个阈值。 优选系统中的第二次升压速度比第一次升压速率慢。 检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。 当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。 根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

公开(公告)号：US5875152A

公开(公告)日：1999-02-23

申请号：US751513

申请日：1996-11-15

申请人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

发明人： Yin-Shang Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Ray-Lin Wan

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  H03K5/1534 ,  G11C8/00 ,  H03K5/22

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C8/18

摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.

摘要翻译： 本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。 公开了一种包括第一和第二电路和间隔定时器的ATD电路。 第一电路具有第一和第二输入和输出。 第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。 作为响应，第一电路的输出从初始第一状态转变到第二状态。 第一电路还响应于第二输入端的复位命令将输出返回到第一状态。 间隔定时器具有耦合到第一电路的第二输入和输入的输出。 响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。 第二电路具有耦合到间隔定时器和输入的输入的输出。 响应于输入端的变化信号的第二电路在输出端产生初始化命令。 该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。 这确保在允许存储器访问之前已经检测到所有地址转换。

公开(公告)号：US5818764A

公开(公告)日：1998-10-06

申请号：US796821

申请日：1997-02-06

申请人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

发明人： Tom D. Yiu ,  I-Long Lee ,  Kuen-Long Chang ,  Han-Sung Chen ,  Tzeng-Huei Shiau ,  Chun-Hsiung Hung ,  Ray-Lin Wan

IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16 ,  G11C16/00

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/16

摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

摘要翻译： 提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。 该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。 块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。 因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

公开(公告)号：US06281719B1

公开(公告)日：2001-08-28

申请号：US09431346

申请日：1999-10-29

申请人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

发明人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

IPC分类号： H03B100

CPC分类号： H03K19/01728 ,  H03K19/00315

摘要： An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit when the threshold is reached.

摘要翻译： 用于集成电路的输出驱动器在内部数据可用之前执行预充电功能，从而最小化这种数据的访问时间。 此外，预充电功能中使用的上拉和下拉电路与输出驱动器分离，并且与要驱动的数据信号的电平无关。 在输出信号被提供给输出焊盘之前，感测电路感测输出焊盘的初始状态，其指示输出焊盘上的电压电平是否高于阈值或低于阈值。 预充电电路包括上拉电路和下拉电路。 上拉电路响应于初始状态，指示输出上的电压电平低于阈值，并且下拉电路响应于初始状态，指示输出上的电压电平高于阈值。 检测器耦合到输出端，产生一个控制信号，指示何时输出接近阈值。 当达到阈值时，逻辑响应来自检测器的控制信号以关闭预充电电路。

公开(公告)号：US6031757A

公开(公告)日：2000-02-29

申请号：US825879

申请日：1997-04-02

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

IPC分类号： G11C16/22 ,  G11C16/04

CPC分类号： G11C16/22

摘要： A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array. Among other functions, the sector protect logic: 1) inhibits sector erase and program operations to a particular sector in response to a set sector lock signal corresponding to the particular sector, and to a first state of control signals in the set of control signals; 2) enables sector erase and program operations in response to a reset sector lock signal corresponding to the particular sector, and to the first state of control signals in the set of control signals; 3) inhibits sector erase and program operations to the particular sector independent of the sector lock signal in response to a second state of control signals in the set of control signals; and 4) enables sector erase and program operations independent of the sector lock signal in response to a third state of control signals in the set of control signals.

摘要翻译： PCT No.PCT / US96 / 18674 Sec。 371日期1997年4月2日 102（e）日期1997年4月2日PCT提交1996年11月22日PCT公布。 第WO98 / 22950号公报 日期1998年5月28日用户可编程写保护方案为集成电路存储器提供灵活性和出色的写保护功能，其包括包括多个扇区的非易失性可擦除和可编程存储器单元的阵列。 命令逻辑检测指示阵列的操作的命令序列，包括程序操作，扇区擦除操作，读取操作，扇区锁定操作和扇区解锁操作。 扇区保护逻辑包括扇区锁定存储器，包括存储阵列中的至少一个扇区的扇区锁定信号的非易失性存储器单元。 在其他功能中，扇区保护逻辑：1）响应于对应于特定扇区的设置扇区锁定信号，以及控制信号组中的控制信号的第一状态，禁止对特定扇区的扇区擦除和编程操作; 2）响应于对应于特定扇区的复位扇区锁定信号和控制信号组中的控制信号的第一状态使能扇区擦除和编程操作; 3）响应于该组控制信号中的控制信号的第二状态，禁止与扇区锁定信号无关的扇区擦除和编程操作到特定扇区; 和4）响应于该组控制信号中的控制信号的第三状态，使扇区擦除和编程操作独立于扇区锁定信号。

公开(公告)号：US5955893A

公开(公告)日：1999-09-21

申请号：US767447

申请日：1996-12-16

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Yin-Shang Liu

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage. The level shifter provides a relatively constant second bias voltage by providing a relatively constant voltage shift V.sub.LS between a level shifter reference voltage V.sub.ref and the bias node. In the present embodiment, this voltage shift V.sub.LS is the absolute value of the gate to source threshold voltage of a FET. Accordingly, the second bias voltage is V.sub.ref -V.sub.LS. In one embodiment, the voltage control circuit includes a second level shifter to provide the first bias voltage.

摘要翻译： 本发明的实施例提供了具有降低的功耗的缓冲电路。 缓冲电路包括耦合到偏置节点处的缓冲器的省电开关。 例如，缓冲器具有适于以TTL电平接收输入电压的输入，并且具有适于在CMOS电平处提供输出电压的输出。 省电开关包括电平转换器和两个耦合到偏置节点的电压控制电路。 缓冲器的输出电压反馈给省电开关。 当输出电压处于低CMOS电平时，省电开关使用电压控制电路向偏置节点提供第一偏置电压。 当输出电压处于高CMOS电平时，省电开关使用电平移位器向偏置节点提供第二偏置电压。 第二偏置电压被选择为使得其在预定的输入截止电压下防止偏置节点和缓冲器之间的电流流动。 电平移位器通过在电平移位器参考电压Vref和偏置节点之间提供相对恒定的电压偏移VLS来提供相对恒定的第二偏置电压。 在本实施例中，该电压偏移VLS是FET的栅极 - 源极阈值电压的绝对值。 因此，第二偏置电压为Vref-VLS。 在一个实施例中，电压控制电路包括提供第一偏置电压的第二电平移位器。

公开(公告)号：US08982640B2

公开(公告)日：2015-03-17

申请号：US13426985

申请日：2012-03-22

申请人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： Chun Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

摘要翻译： 非易失性存储器阵列被分成多个存储器组。 非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。 控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。 通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

公开(公告)号：US08797802B2

公开(公告)日：2014-08-05

申请号：US13536555

申请日：2012-06-28

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

摘要翻译： 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US20130326184A1

公开(公告)日：2013-12-05

申请号：US13584393

申请日：2012-08-13

申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储器单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。