公开(公告)号：US07678510B2

公开(公告)日：2010-03-16

申请号：US11017196

申请日：2004-12-21

申请人： Naoyuki Ishiwata ,  Koji Hosono

发明人： Naoyuki Ishiwata ,  Koji Hosono

IPC分类号： G03F1/00

CPC分类号： G03F1/44 ,  G03F1/30 ,  G03F1/80

摘要： There is provided a method of manufacturing a mask for exposure, which is capable of measuring the phase difference between a shifter portion and a non-shifter portion with good accuracy.A mask for exposure having: two first light-shielding device patterns, which are formed on a quartz substrate (transparent substrate) in a device region at a first gap and extend over a first concave portion; a second device light-shielding pattern at a second gap from the first device light-shielding pattern; two first light-shielding monitor patterns, which are formed on the quartz substrate in a monitor region at a third gap wider than the first gap and extend over a second concave portion; and second light-shielding monitor pattern, which has a fourth gap wider than the second gap from the first light-shielding monitor pattern, in which the size of the first light-shielding monitor pattern is equal to or less than the size of the first light-shielding device pattern.

摘要翻译： 提供一种制造用于曝光的掩模的方法，其能够以高精度测量移位部分和非移动部分之间的相位差。 一种用于曝光的掩模，具有：在第一间隙的器件区域中在石英衬底（透明衬底）上形成并在第一凹部上延伸的两个第一光屏蔽器件图案; 在与第一器件遮光图案的第二间隙处的第二器件遮光图案; 两个第一光屏蔽监视器图案，其形成在监视器区域中的石英衬底上，第三间隙比第一间隙宽，并延伸到第二凹部; 以及第二遮光监视器图案，其具有比第一遮光监视器图案的第二间隙宽的第四间隙，其中第一遮光监视器图案的尺寸等于或小于第一遮光监视器图案的尺寸 遮光装置图案。

公开(公告)号：US07609558B2

公开(公告)日：2009-10-27

申请号：US11530347

申请日：2006-09-08

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642

摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

摘要翻译： 非易失性半导体存储器件包括具有串联连接的多个多电平存储单元的存储单元阵列。 多个多级存储器单元形成多个阈值分布，每个阈值分布对应于较低位的状态和高位的状态，其中低位和高位分别构成下部页面和上部页面 。 较低位的状态将阈值分布分为两组，高位的状态进一步将两组中的每一组进行二分。 当对上部页面的存储单元进行编程时，当对下部页面的存储单元进行编程时，较高电位被施加到与所选字线相邻的未选择字线，而不是应用于未选择的字线。

公开(公告)号：US20090244978A1

公开(公告)日：2009-10-01

申请号：US12408260

申请日：2009-03-20

申请人： Masahiro Yoshihara ,  Toshiaki Edahiro ,  Koji Hosono

发明人： Masahiro Yoshihara ,  Toshiaki Edahiro ,  Koji Hosono

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C7/065 ,  G11C7/067 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  G11C2207/068

摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.

摘要翻译： 半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。 感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管 以不通过第一和第二感测节点在位线中提供电流。

公开(公告)号：US07561468B2

公开(公告)日：2009-07-14

申请号：US11857091

申请日：2007-09-18

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V1 than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V2 than the lower voltage (V1

摘要翻译： 器件具有数据写入模式以升高包含非写入选择存储单元的第一升压沟道区和位于更接近第一选择栅晶体管的非选择存储单元，以及包含未选择存储器的第二升压沟道区 位于比选择的存储单元更靠近第二选择栅极晶体管的单元，彼此电分离。 在该模式中，施加到第二选择栅极晶体管旁边的未选择的存储单元的写入非选择电压至少两级在施加于其它的写入非选择电压Vm的较低电压V1之间切换 NAND单元单元中的未选择存储单元和比低电压（V1

公开(公告)号：US07524591B2

公开(公告)日：2009-04-28

申请号：US11126295

申请日：2005-05-11

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G03F1/00 ,  G03C5/00

CPC分类号： G03F1/50

摘要： A photomask made by using a negative photoresist includes a transparent substrate defined with a device chip area, an opaque device pattern formed on the transparent substrate in the device chip area, and a dummy opaque pattern provided on the transparent substrate outside of the device chip area.

摘要翻译： 通过使用负性光致抗蚀剂制成的光掩模包括由器件芯片区域限定的透明衬底，在器件芯片区域中形成在透明衬底上的不透明器件图案，以及设置在器件芯片区域外部的透明衬底上的虚设不透明图案 。

公开(公告)号：US20090010039A1

公开(公告)日：2009-01-08

申请号：US12132972

申请日：2008-06-04

申请人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

发明人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/72

摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

公开(公告)号：US20080291716A1

公开(公告)日：2008-11-27

申请号：US12123827

申请日：2008-05-20

申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C11/00

CPC分类号： G11C11/36

摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

公开(公告)号：US20080225618A1

公开(公告)日：2008-09-18

申请号：US12123157

申请日：2008-05-19

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C7/06

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US07315915B2

公开(公告)日：2008-01-01

申请号：US10950416

申请日：2004-09-28

申请人： Yasuyuki Fukuda ,  Masatsugu Kojima ,  Kenichi Imamiya ,  Koji Hosono

发明人： Yasuyuki Fukuda ,  Masatsugu Kojima ,  Kenichi Imamiya ,  Koji Hosono

IPC分类号： G06F12/00

CPC分类号： G11C16/16

摘要： A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein, the cell array being divided into a plurality of blocks, each the block being divided into a plurality of sub-blocks each having one or plural and continuous pages; and a controller for controlling data erasure of the cell array in a way that each the sub-block serves as a unit of data erasure, wherein each the sub-block in the cell array stores the number of data erasure which is renewed by each data erasure, and the number of data erasure is limited for each the sub-block to a permissible maximum value stored in a certain block in the cell array.

摘要翻译： 非挥发性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储器单元的单元阵列，所述单元阵列被划分为多个块，每个块被分成多个子块，每个子块具有一个 或多个和连续的页面; 以及用于以每个子块用作数据擦除单位的方式控制单元阵列的数据擦除的控制器，其中单元阵列中的每个子块存储由每个数据更新的数据擦除次数 并且将每个子块的数据擦除的数量限制为存储在单元阵列中的某个块中的允许的最大值。

公开(公告)号：US20070206399A1

公开(公告)日：2007-09-06

申请号：US11682478

申请日：2007-03-06

申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。