公开(公告)号：US20080256275A1

公开(公告)日：2008-10-16

申请号：US12049323

申请日：2008-03-15

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F13/00

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US20080235647A1

公开(公告)日：2008-09-25

申请号：US12130268

申请日：2008-05-30

申请人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

发明人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

公开(公告)号：US07409520B2

公开(公告)日：2008-08-05

申请号：US11042692

申请日：2005-01-25

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US07398482B2

公开(公告)日：2008-07-08

申请号：US11191580

申请日：2005-07-28

申请人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

发明人： Harm Peter Hofstee ,  James Allan Kahle ,  Takeshi Yamazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

公开(公告)号：US07392511B2

公开(公告)日：2008-06-24

申请号：US10670824

申请日：2003-09-25

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

IPC分类号： G06F9/45

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.

摘要翻译： 一个程序进入至少两个对象文件：一个对象文件，用于每个受支持的处理器环境。 在编译过程中，将数据位置，计算强度和数据并行等代码特征分析并记录在目标文件中。 在运行时间期间，代码特征与运行时考虑相结合，例如处理器上的当前负载和正在处理的数据的大小，以达到总体值。 然后，总体值用于确定哪些处理器将被分配任务。 这些值基于各种处理器的特性分配。 例如，如果一个处理器更好地处理针对大量数据流的密集计算，则高度计算密集的程序和处理大量数据的程序对该处理器进行加权。 然后在分配的处理器上加载和执行相应的对象。

公开(公告)号：US07200688B2

公开(公告)日：2007-04-03

申请号：US10448237

申请日：2003-05-29

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.

摘要翻译： 本发明在计算机系统中提供异步DMA命令完成通知。 生成与多个DMA命令相关联的命令标签。 具有命令标签的DMA数据移动命令与具有命令标签的另一DMA数据移动命令分组。 监视属于同一标签组的DMA命令，以查看相同标签组的所有DMA命令是否完成。

公开(公告)号：US07093080B2

公开(公告)日：2006-08-15

申请号：US10682386

申请日：2003-10-09

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0835

摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

公开(公告)号：US06865631B2

公开(公告)日：2005-03-08

申请号：US09736582

申请日：2000-12-14

申请人： Harm Peter Hofstee ,  Ravi Nair

发明人： Harm Peter Hofstee ,  Ravi Nair

IPC分类号： G06F13/24 ,  G06F13/22 ,  G06F13/28

CPC分类号： G06F13/24

摘要： A method and system for executing one or more remote procedure calls. In one embodiment, a method comprises the step of a processing unit issuing a plurality of commands to a corresponding DMA controller. One or more commands of the plurality of commands issued by the processing unit are to copy attached processing unit instructions associated with one or more Attached Processing Unit's (APU's) and data associated with the attached processing unit instructions from the shared memory to one or more APU's. The attached processing unit instructions may include instructions that enable the associated one or more APU's to perform one or more particular operations on the data. The method further comprises the DMA controller issuing an indication to the one or more APU's to perform the one or more operations on the data associated with the attached processing unit instructions. Instead of having the particular APU that completed its operation notify the corresponding processing unit of its completion of the operation, the DMA controller polls a status line of each of the one or more attached processing units to determine if any of the one or more attached processing units completed its operation. The DMA controller then copies the results of the operations after each of the one or more attached processing units completes its operation.

摘要翻译： 一种用于执行一个或多个远程过程调用的方法和系统。 在一个实施例中，一种方法包括处理单元向相应的DMA控制器发出多个命令的步骤。 由处理单元发出的多个命令的一个或多个命令是将与一个或多个附属处理单元（APU）相关联的附加处理单元指令和与附加处理单元指令相关联的附加处理单元指令从共享存储器复制到一个或多个APU 。 附加的处理单元指令可以包括使得相关联的一个或多个APU能够对数据执行一个或多个特定操作的指令。 该方法还包括DMA控制器向一个或多个APU发出指示以对与所附加的处理单元指令相关联的数据执行一个或多个操作。 DMA控制器不是使完成其操作的特定APU通知对应的处理单元完成操作，而是DMA控制器轮询一个或多个附加的处理单元中的每一个的状态行，以确定是否有一个或多个附加处理 单位完成运作。 然后，DMA控制器在每个一个或多个附加处理单元完成其操作之后复制操作的结果。

公开(公告)号：US06826110B2

公开(公告)日：2004-11-30

申请号：US10273567

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.

摘要翻译： 在多端口存储器阵列的存储器块中提供用于具有减少读取字线数量的数据读出的改进的单元电路。 通过在读取的字线和单元电路中的多路复用器之间使用解码器来显着减少读取字线的数量。 存储块具有多个地址输入并存储多个写入数据信号。 在单元电路中，解码器接收地址输入的子集作为解码器输入并输出多个选择信号。 复用器耦合到解码器以接收选择信号，并且基于选择信号选择写入数据信号之一。 此外，读取的字线被耦合到解码器，用于将地址输入的子集携带到解码器。

公开(公告)号：US06785841B2

公开(公告)日：2004-08-31

申请号：US09734371

申请日：2000-12-14

申请人： Chekib Akrout ,  Harm Peter Hofstee ,  James Allan Kahle

发明人： Chekib Akrout ,  Harm Peter Hofstee ,  James Allan Kahle

IPC分类号： G06F1100

CPC分类号： G06F11/2043 ,  G06F11/2028 ,  G06F11/2038

摘要： A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.

摘要翻译： 公开了一种包括中央处理器和多个附属处理器的系统，其全部在单个管芯上。 每个连接的处理器优选地在功能上等同于其他附加处理器中的每一个。 该系统还包括可连接到中央处理器的至少一个冗余处理器。 冗余处理器可以基本上等同于附接的每个处理器。 一旦检测到所附加的处理器之一的故障，则该系统被配置为禁用非功能处理器并启用冗余处理器。 连接的处理器可以经由并行总线或流水线总线连接到存储器接口单元，其中每个连接的处理器连接到流水线总线的级。 附加的处理器可以各自包括适于执行数学功能的加载/存储单元和逻辑。