公开(公告)号：US20120139085A1

公开(公告)日：2012-06-07

申请号：US12958429

申请日：2010-12-02

申请人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L29/38 ,  H01L21/3213

CPC分类号： H01L29/02 ,  H01L21/76254

摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

摘要翻译： 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

公开(公告)号：US20120119310A1

公开(公告)日：2012-05-17

申请号：US12944174

申请日：2010-11-11

申请人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/49 ,  H01L21/285

CPC分类号： H01L29/49 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

摘要翻译： 公开了一种在晶体管上制造体接触的结构和方法。 该方法包括在处理晶片上形成具有晶体管的半导体结构。 然后将结构反转，并移除手柄晶片。 然后在倒置位置的晶体管上形成硅化物体接触。 身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

公开(公告)号：US20120119302A1

公开(公告)日：2012-05-17

申请号：US12944018

申请日：2010-11-11

申请人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

发明人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

IPC分类号： H01L23/532 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/76879 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76805 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

摘要翻译： 提供一种电结构，其包括存在于半导体衬底上的电介质层和通过电介质层存在的通路开口。 在通孔开口内存在互连。 在半导体衬底中存在金属半导体合金接触。 金属半导体合金触点具有由相对于通孔开口的中心线的凸曲面限定的周长。 限定金属半导体合金触点的凸曲率的端点与通孔开口的侧壁，互连的侧壁和半导体衬底的上表面之间的界面对准。

公开(公告)号：US20120068237A1

公开(公告)日：2012-03-22

申请号：US12886224

申请日：2010-09-20

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

摘要翻译： 在替代栅极集成方案中形成平坦化介电层之后，去除一次性栅极结构，并且在凹入的栅极区内形成栅极电介质层和栅极电极层的堆叠。 然后，每个栅极电极结构凹陷在栅极电介质层的最上表面之下。 通过平面化形成在每个栅电极上方的介电金属氧化物部分。 电介质金属氧化物部分和栅极间隔物用作自对准蚀刻掩模与图案化的光致抗蚀剂组合以在每个嵌入的存储器单元结构中暴露和金属化源极区域和内部电极的半导体表面。 金属化半导体部分形成金属半导体合金带，其在电容器的内部电极和存取晶体管的源之间提供导电路径。

公开(公告)号：US20110309474A1

公开(公告)日：2011-12-22

申请号：US12818448

申请日：2010-06-18

申请人： Chengwen Pei ,  Xi Li ,  Geng Wang

发明人： Chengwen Pei ,  Xi Li ,  Geng Wang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/3065 ,  H01L27/1087 ,  H01L29/36 ,  H01L29/66181

摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.

摘要翻译： 公开了一种沟槽和制造方法。 沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。 然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

公开(公告)号：US20110272762A1

公开(公告)日：2011-11-10

申请号：US12776829

申请日：2010-05-10

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

摘要翻译： 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

公开(公告)号：US20110193193A1

公开(公告)日：2011-08-11

申请号：US12704084

申请日：2010-02-11

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US07759766B2

公开(公告)日：2010-07-20

申请号：US11843047

申请日：2007-08-22

申请人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

发明人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.

摘要翻译： 薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。 在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。 本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。 与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。 与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

公开(公告)号：US09484269B2

公开(公告)日：2016-11-01

申请号：US12822492

申请日：2010-06-24

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L21/762 ,  H01L27/108

CPC分类号： H01L21/84 ,  H01L21/76237 ,  H01L27/10847 ,  H01L27/1203

摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

摘要翻译： 半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。 一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。 掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

公开(公告)号：US09048339B2

公开(公告)日：2015-06-02

申请号：US13606448

申请日：2012-09-07

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.

摘要翻译： 提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。 该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂 散装衬底形成掩埋板。 该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部， 去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。