公开(公告)号：US5496761A

公开(公告)日：1996-03-05

申请号：US456660

申请日：1995-06-02

Applicant: Enrico M. A. Ravanelli ,  Flavio Villa

Inventor： Enrico M. A. Ravanelli ,  Flavio Villa

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/761

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7801 ,  H01L29/7817

Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket--isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

Abstract translation: 集成器件包括隔离导电类型的区域，每个区域围绕具有相反导电类型的外延阱，并且容纳漏极和源极区域，并且覆盖有容纳栅极区域的氧化物层，并且在其上延伸源极，漏极和 门连接。 为了线性化外延袋隔离区域结处的电位分布并且靠近连接下方的源极区域，这些区域设置有嵌入在氧化物层中的双链冷凝器，并且其中间元件被偏置到 预定电位

公开(公告)号：US5434445A

公开(公告)日：1995-07-18

申请号：US47965

申请日：1993-04-15

Applicant: Enrico M. A. Ravanelli ,  Flavio Villa

Inventor： Enrico M. A. Ravanelli ,  Flavio Villa

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/41 ,  H01L29/772

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7801 ,  H01L29/7817

Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket-isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

Abstract translation: 集成器件包括隔离导电类型的区域，每个区域围绕具有相反导电类型的外延阱，并且容纳漏极和源极区域，并且覆盖有容纳栅极区域的氧化物层，并且在其上延伸源极，漏极和 门连接。 为了线性化外延袋隔离区域结处的电位分布并且靠近连接下方的源极区域，这些区域设置有嵌入在氧化物层中的双链冷凝器，并且其中间元件被偏置到 预定电位。

公开(公告)号：US5045910A

公开(公告)日：1991-09-03

申请号：US381340

申请日：1989-07-17

Applicant: Flavio Villa

Inventor： Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/732 ,  H03F1/30 ,  H03F1/52 ,  H03F3/04 ,  H03F3/343 ,  H03F3/347 ,  H03F3/68 ,  H03K17/00 ,  H03K17/08 ,  H03K17/0812 ,  H03K17/12

CPC classification number: H03K17/12 ,  H03K17/08126 ,  H03K2017/0806 ,  H03K2217/0036

Abstract: An integrated power transistor with reduced sensitivity to thermal stresses and improved resistance to direct secondary breakdown, comprising a plurality of transistors having their emitter regions connected so as to define a common emitter terminal, their collector regions connected so as to define a common collector region, and the same plurality of diodes connected to the respective transistors to form therewith a current mirror circuit, each base of the transistors being connected to the first terminal of a corresponding resistor, the second terminal of the corresponding resistors being connected to a common base.

公开(公告)号：US4886982A

公开(公告)日：1989-12-12

申请号：US135220

申请日：1987-12-21

Applicant: Flavio Villa ,  Giovanni Siepe

Inventor： Flavio Villa ,  Giovanni Siepe

IPC: H01L21/331 ,  H01L23/58 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H03F1/42 ,  H03F1/52

CPC classification number: H03K17/14 ,  H01L27/0821 ,  H01L29/7304

Abstract: This power transistor comprises a plurality of elementary transistors, also indicated as "fingers", having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base terminals connected to at least one current source. Each elementary transistor is part of a circuit comprising a diode forming, together with the elementary transistor, a current mirror, so that the collector current passing through the elementary transistor is far less sensitive to the temperature gradients which originate inside the power transistor.

Abstract translation: 该功率晶体管包括多个基本晶体管，也称为“指状”，其发射极端子相互连接并形成公共发射极端子，集电极端子也相互连接并形成公共集电极端子，基极端子连接至少一个 当前来源。 每个基本晶体管是包括二极管的电路的一部分，该二极管与基本晶体管一起形成电流镜，使得通过基本晶体管的集电极电流对于功率晶体管内的温度梯度的敏感性要小得多。

公开(公告)号：US4783693A

公开(公告)日：1988-11-08

申请号：US885503

申请日：1986-07-14

Applicant: Angelo Alzati ,  Flavio Villa

Inventor： Angelo Alzati ,  Flavio Villa

IPC: H01L21/8222 ,  H01L27/06 ,  H01L27/07 ,  H01L27/082 ,  H02P7/00 ,  H01L29/72 ,  H01L27/10 ,  H01L29/48

CPC classification number: H01L29/7302 ,  G11B5/022 ,  H01L27/0766 ,  H01L27/0823 ,  H02P7/03

Abstract: This driver element for inductive loads, specifically DC motors, step motors, solenoids, and the like comprises a transistor bridge, each transistor of the bridge being parallel connected to a respective flyback diode ensuring recirculation of the current on switching the transistors off. The diodes are of the Schottky type, so as to ensure reduced switching loss and improved reliability of the element. The Schottky diodes are formed by leaving a non-diffused portion of the collector epitaxial layer through the base and emitter regions up to the device surface so as to contact the emitter metallization layer.

Abstract translation: 用于感性负载的驱动元件，特别是直流电动机，步进电动机，螺线管等包括晶体管桥，桥的每个晶体管并联连接到相应的反激二极管，确保在关闭晶体管时电流的再循环。 二极管为肖特基型，以确保元件的开关损耗降低和可靠性得到改善。 通过将集电极外延层的非扩散部分通过基极和发射极区域直到器件表面形成以便与发射极金属化层接触来形成肖特基二极管。

公开(公告)号：US4682197A

公开(公告)日：1987-07-21

申请号：US812109

申请日：1985-12-23

Applicant: Flavio Villa ,  Bruno Murari ,  Franco Bertotti ,  Aldo Torazzina ,  Fabrizio Stefani

Inventor： Flavio Villa ,  Bruno Murari ,  Franco Bertotti ,  Aldo Torazzina ,  Fabrizio Stefani

IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L27/102 ,  H01L29/73 ,  H01L29/72 ,  H01L23/52 ,  H01L27/10 ,  H01L29/08

CPC classification number: H01L27/0211 ,  H01L27/1024

Abstract: This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.

Abstract translation: 该集成半导体器件旨在大大减少直接二次击穿现象，并且具有形成交叉结构的多个并排基本晶体管。 为了减小基本晶体管之间的热相互作用，后者彼此间隔开大约等于一个基本晶体管的宽度的距离，并由电流源驱动。 间距减少电热相互作用。 此外，为了最小化器件面积要求，使任何两个相邻基本晶体管之间的空间适合作为电流源工作的驱动晶体管，或者是器件形成B类输出级的补充级的基本晶体管， 输出晶体管交替接通。