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    Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit
    61.
    发明授权
    Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit 失效
    具有时钟控制功能的管道算术和逻辑系统，用于选择性地为给定单元提供时钟

    公开(公告)号：US5771376A

    公开(公告)日：1998-06-23

    申请号：US725495

    申请日：1996-10-04

    申请人： Hiroshi Hayakawa ,  Harutsugu Fukumoto ,  Hiroaki Tanaka

    发明人： Hiroshi Hayakawa ,  Harutsugu Fukumoto ,  Hiroaki Tanaka

    IPC分类号： G06F9/312 ,  G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/325 ,  G06F9/3867 ,  G06F9/3869

    摘要： A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.

    摘要翻译： 一种管道算术和逻辑系统，其能够在不使用NOP指令的情况下调整阶段之间的操作定时，从而提供其控制部分的尺寸减小。 该系统具有解码器组，其包括被分成用于控制算术部分单元的解码器组，寄存器文件单元和程序计数器单元的解码器组，以及用于控制地址单元的解码器，还包括由 地址单元控制解码器。 来自外部源的时钟信号直接馈送到地址单元，同时通过时钟控制单元馈送到其它单元。 当获取数据传输指令并重复执行MA阶段两次时，系统在执行第一MA级停止时钟控制单元以禁止地址单元以外的单元的操作。

    Neural network learning device
    62.
    发明授权
    Neural network learning device 失效
    神经网络学习装置

    公开(公告)号：US5727131A

    公开(公告)日：1998-03-10

    申请号：US139710

    申请日：1993-10-22

    申请人： Joji Nakamura ,  Hiroaki Tanaka ,  Tomohisa Yoshimi ,  Takayoshi Kawai ,  Yuji Ito ,  Yuji Takeo

    发明人： Joji Nakamura ,  Hiroaki Tanaka ,  Tomohisa Yoshimi ,  Takayoshi Kawai ,  Yuji Ito ,  Yuji Takeo

    IPC分类号： G06F15/18 ,  G06G7/60 ,  G06N3/04 ,  G06N3/08 ,  G06N99/00 ,  G06E1/00 ,  G06E3/00

    CPC分类号： G06N3/0454 ,  G06N3/08

    摘要： A learning device that affects only the input-output relationships that should be additionally learned. A learning NN unit 8 capable of executing additional learning is provided separately from a learned NN unit 4 which is a basic control unit. The learned NN unit 4 produces a basic output in response to an input signal from a signal input unit 14, the learning NN unit 8 produces a correction amount desired by an individual person, and a desired control is performed based on the total value. When the output is changed, a difference is calculated between the changed output value and the basic output value from a first output unit 15, and the learning NN unit 8 executes the additional learning based upon the difference and the input value at this moment in compliance with a back-propagation method.

    摘要翻译： 仅影响应该额外学习的输入 - 输出关系的学习设备。 与作为基本控制单元的学习NN单元4分开提供能够执行附加学习的学习NN单元8。 所学习的NN单元4响应于来自信号输入单元14的输入信号产生基本输出，学习NN单元8产生个人期望的校正量，并且基于总值执行期望的控制。 当输出改变时，在改变的输出值和来自第一输出单元15的基本输出值之间计算差值，并且学习NN单元8基于此时的差异和输入值执行附加学习 具有反向传播方法。

    Mixer
    63.
    发明授权
    Mixer 失效
    混合器

    公开(公告)号：US5717364A

    公开(公告)日：1998-02-10

    申请号：US734468

    申请日：1996-10-17

    申请人： Mitsuo Ariie ,  Hiroaki Tanaka

    发明人： Mitsuo Ariie ,  Hiroaki Tanaka

    IPC分类号： H03D7/12 ,  H03D7/14 ,  H03B21/00 ,  H03C3/00 ,  H04B1/28

    CPC分类号： H03D7/1441 ,  H03D7/125 ,  H03D7/1458 ,  H03D2200/0043 ,  H03D2200/0088 ,  H03D7/14

    摘要： A small and inexpensive mixer that does not require a choke inductor and a large-capacitance capacitor. The mixer has a FET. The FET's source is grounded via a capacitor and is also connected to a power-supply terminal. The FET's gate is coupled to a bias voltage and also connected to a gate input terminal via a capacitor. The FET's drain is connected to an output terminal via a capacitor. A modulating signal is input into the power-supply terminal, and a local signal is input into the gate input terminal, so that a modulated signal is output from the output terminal.

    摘要翻译： 一种不需要扼流圈电感器和大容量电容器的小型廉价混频器。 混频器有一个FET。 FET的源极通过电容器接地，并且还连接到电源端子。 FET的栅极耦合到偏置电压，并且还经由电容器连接到栅极输入端子。 FET的漏极通过电容器连接到输出端子。 调制信号被输入到电源端子中，并且本地信号被输入到栅极输入端子中，从而从输出端子输出调制信号。

    Sense amplifier for receiving read outputs from a semiconductor memory array
    64.
    发明授权
    Sense amplifier for receiving read outputs from a semiconductor memory array 失效
    用于从半导体存储器阵列接收读出输出的读出放大器

    公开(公告)号：US5422854A

    公开(公告)日：1995-06-06

    申请号：US104912

    申请日：1993-08-12

    申请人： Tetsuo Hirano ,  Takahiro Yanagi ,  Hiroaki Tanaka

    发明人： Tetsuo Hirano ,  Takahiro Yanagi ,  Hiroaki Tanaka

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C16/28

    摘要： Output signals, representing data read out from a memory cell array comprising a plurality of memory cells arranged in a matrix of m rows and n columns, each cell comprising an EPROM transistor, are fed to a sense amplifier. A row of the memory cell array is selected by signals SRl-SRm coming from a row decoder. The output of the selected row is taken out by a column select transistor selected by signals SCl-SCn from a column decoder before being fed to the sense amplifier. The sense amplifier comprises a memory cell output detecting circuit having a first load transistor for receiving output read out from the memory cell array and a dummy cell output detecting circuit having a second load transistor to which dummy cell equivalent to the memory cell is connected. The circuit of the first load transistor and that of the second load transistor form a current mirror circuit. The sense amplifier also comprises a sense amplifier output evaluation circuit having differential amplifiers which transmit output voltages of the memory cell output detecting circuit and of the dummy cell output detecting circuit to reflect the respective currents running through the first and second load transistors.

    摘要翻译： 输出信号，表示从包括以m行和n列的矩阵排列的多个存储单元的存储单元阵列读出的数据，每个单元包括EPROM晶体管，被馈送到读出放大器。 存储单元阵列的一行由来自行解码器的信号SR1-SRm选择。 所选行的输出在被馈送到读出放大器之前由列解码器由信号SCl-SCn选择的列选择晶体管取出。 读出放大器包括：存储单元输出检测电路，具有用于接收从存储单元阵列读出的输出的第一负载晶体管;以及具有第二负载晶体管的虚设单元输出检测电路，虚拟单元与该存储单元相连。 第一负载晶体管和第二负载晶体管的电路形成电流镜电路。 读出放大器还包括具有差分放大器的读出放大器输出评估电路，差分放大器传输存储单元输出检测电路和虚拟单元输出检测电路的输出电压，以反映通过第一和第二负载晶体管流过的相应电流。

    Zirconia ceramics
    66.
    发明授权
    Zirconia ceramics 失效
    氧化锆陶瓷

    公开(公告)号：US5279995A

    公开(公告)日：1994-01-18

    申请号：US38051

    申请日：1993-03-25

    申请人： Hiroaki Tanaka ,  Yutaka Kimura ,  Masamichi Obitsu

    发明人： Hiroaki Tanaka ,  Yutaka Kimura ,  Masamichi Obitsu

    IPC分类号： C04B35/486 ,  C04B35/48

    CPC分类号： C04B35/486

    摘要： A zirconia ceramic composed of crystals which scarcely undergo phase transformation from tetragonal system to monoclinic in the temperature range of from 100.degree. C. to 300.degree. C. even in the presence of water vapor or water is disclosed, said zirconia ceramic comprising at least 93% by weight of partially stabilized zirconia mainly composed of tetragonal crystals and containing mainly Y.sub.2 O.sub.3 and ZrO.sub.2 at the former to the latter molar ratio of from 2/98 to 4.5/95.5 and balance of at least one of the oxides selected from the group consisting of boron oxide, germanium oxide, and gallium oxide, wherein the content of the boron oxide is 1% by weight or less.

    摘要翻译： 公开了一种由晶体组成的氧化锆陶瓷，即使在水蒸汽或水的存在下也几乎不会在从100度到300度的温度范围内从四方晶相转变为单斜晶系，所述氧化锆陶瓷包含至少93 主要由四方晶体组成并且主要含有Y 2 O 3和ZrO 2的部分稳定化的氧化锆的重量百分数，其中后者的摩尔比为2/98至4.5 / 95.5，余量为至少一种选自以下的氧化物： 氧化硼，氧化锗和氧化镓，其中氧化硼的含量为1重量％以下。

    Substrate potential adjusting apparatus
    67.
    发明授权
    Substrate potential adjusting apparatus 失效
    基板电位调节装置

    公开(公告)号：US5264808A

    公开(公告)日：1993-11-23

    申请号：US841535

    申请日：1992-02-26

    申请人： Hiroaki Tanaka

    发明人： Hiroaki Tanaka

    IPC分类号： G11C11/413 ,  G05F3/20 ,  G11C11/403 ,  G11C11/408 ,  H03K3/03 ,  H03B5/24 ,  H03K3/01

    CPC分类号： G05F3/205 ,  H03K3/0315

    摘要： A substrate potential adjusting apparatus of the invention includes: a pump circuit for drawing a current from a semiconductor substrate to adjust a substrate potential; ring oscillators for supplying a periodical signal to the pump circuit and causing the pump circuit to operate; a limiter circuit for detecting a potential of the semiconductor substrate and controlling to switch between operation and non-operation of the ring oscillators in accordance with the detected potential; and a selector circuit for changing the oscillation period of the periodical signal outputted from the ring oscillators in accordance with a signal inputted externally from a chip, the signal determining an operation mode of a circuit formed on the semiconductor substrate.

    摘要翻译： 本发明的衬底电位调节装置包括：泵电路，用于从半导体衬底吸取电流以调整衬底电位; 环形振荡器，用于向泵电路提供周期性信号并使泵电路工作; 限制电路，用于根据检测到的电位检测半导体衬底的电位并控制环形振荡器的工作和非操作之间的切换; 以及选择器电路，用于根据从芯片外部输入的信号来改变从环形振荡器输出的周期信号的振荡周期，该信号确定形成在半导体衬底上的电路的操作模式。

    High frequency band-pass filter
    70.
    发明授权
    High frequency band-pass filter 失效
    高频带通滤波器

    公开(公告)号：US4816788A

    公开(公告)日：1989-03-28

    申请号：US68439

    申请日：1987-06-30

    申请人： Youhei Ishikawa ,  Hiroaki Tanaka

    发明人： Youhei Ishikawa ,  Hiroaki Tanaka

    IPC分类号： H01P1/203 ,  H01P1/205 ,  H03H11/10

    CPC分类号： H01P1/20336 ,  H01P1/20381

    摘要： A high frequency band-pass filter which includes a single resonator or a plurality of resonators adapted to pass a high frequency signal of a predetermined frequency band region, and an active element device electrically coupled with one or the plurality of the resonators so as to present a negative resistance when the resonator is in a resonant state.

    摘要翻译： 一种高频带通滤波器，其包括适于通过预定频带区域的高频信号的单个谐振器或多个谐振器，以及与一个或多个谐振器电耦合的有源元件装置，以便呈现 当谐振器处于谐振状态时的负电阻。