公开(公告)号：US5750781A

公开(公告)日：1998-05-12

申请号：US485143

申请日：1995-06-07

申请人： Yoshifumi Yoshida ,  Akira Tanigawa ,  Satoshi Yamamoto

发明人： Yoshifumi Yoshida ,  Akira Tanigawa ,  Satoshi Yamamoto

IPC分类号： C08F2/10 ,  C08F20/52 ,  C08F26/02 ,  C08F220/56 ,  C08F226/04 ,  C07C231/12

CPC分类号： C08F220/56 ,  C08F226/04

摘要： A process for preparing an aqueous solution of an ionic copolymer having a copolymer concentration of 20 % by weight or less and a viscosity of 20 ps or more at 25.degree. C. which comprises conducting copolymerization of an acrylamide compound(B) with a diallylamine compound(A) by continuously adding an aqueous solution of (B) having a concentration of 30% by weight or less to an aqueous solution of the diallylamine compound(A) having a concentration of 5% by weight or more and less than 10% by weight, and this process exhibit high conversion of diallylamine compounds, of which reactivity is low, and a copolymer having a high molecular weight can be obtained.

摘要翻译： 一种在25℃下制备共聚物浓度为20重量％以下且粘度为20ps以上的离子共聚物的水溶液的方法，其包括使丙烯酰胺化合物（B）与二烯丙基胺化合物 （A）通过将浓度为30重量％以下的（B）的水溶液连续添加到浓度为5重量％以上且小于10体积％的二烯丙基胺化合物（A）的水溶液中，通过 重量，并且该方法表现出高反应性的二烯丙基胺化合物的高转化率，并且可以获得具有高分子量的共聚物。

公开(公告)号：US08499443B2

公开(公告)日：2013-08-06

申请号：US12984188

申请日：2011-01-04

申请人： Yoshifumi Yoshida

发明人： Yoshifumi Yoshida

IPC分类号： H05K3/20 ,  H04R17/10

CPC分类号： H03H9/1021 ,  H01L2924/0002 ,  H03H2003/022 ,  Y10T29/42 ,  Y10T29/49002 ,  Y10T29/49147 ,  Y10T29/49151 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49798 ,  H01L2924/00

摘要： A package manufacturing method capable of easily manufacturing a penetration electrode-attached base board having excellent shape accuracy with a high degree of flatness without forming cracks or the like is provided. The package manufacturing method includes an insertion hole forming step of forming insertion holes in one surface of a base board wafer so as not to penetrate through the base board wafer; a core portion insertion step of inserting conductive core portions made of a metal material into the insertion holes; a welding step of heating the base board wafer to a temperature higher than the softening point of the glass material so as to weld the base board wafer to the core portions while holding the one surface side of the base board wafer with a receiving mold and pressing the other surface of the base board wafer with a flat pressurizing mold; a cooling step of cooling the base board wafer; and a polishing step of polishing both surfaces of the base board wafer.

摘要翻译： 提供了一种能够容易地制造具有高平坦度而具有优异形状精度而不形成裂缝等的具有穿透电极的基板的封装制造方法。 封装制造方法包括：插入孔形成步骤，在基板晶片的一个表面上形成插入孔，以便不穿透基板晶片; 芯部插入步骤，将由金属材料制成的导电芯部插入插入孔中; 将基板晶片加热到高于玻璃材料的软化点的温度的焊接步骤，以将基板晶片焊接到芯部，同时用接收模具保持基板晶片的一个表面侧，并且按压 基板晶片的另一个表面具有平坦的加压模具; 冷却基板晶片的冷却步骤; 以及研磨基板晶片的两面的研磨工序。

公开(公告)号：US20130057355A1

公开(公告)日：2013-03-07

申请号：US13566037

申请日：2012-08-03

申请人： Yoshifumi Yoshida

发明人： Yoshifumi Yoshida

IPC分类号： H01L41/053 ,  H03B5/32

CPC分类号： H03H9/0519 ,  H03H9/1021

摘要： A piezoelectric vibration device is provided that can reduce the stress and strain that transmit through a base substrate. The piezoelectric vibration device includes a piezoelectric vibrating reed that oscillates in an AT mode, and that includes excitation electrodes respectively formed on the front and back surfaces of the reed. One of the excitation electrodes is connected to the base substrate via a metal bump on a center line passing across the shorter sides of the piezoelectric vibrating reed and in the vicinity of one of the shorter sides of the piezoelectric vibrating reed. The other excitation electrode is connected to the base substrate via a metal bump on the same side as the above shorter side, and in the vicinity of a portion where the shorter side of the piezoelectric vibrating reed crosses one of the longer sides of the piezoelectric vibrating reed.

摘要翻译： 提供了一种可以减少通过基底衬底传播的应力和应变的压电振动装置。 压电振动装置包括以AT模式振荡的压电振动片，其包括分别形成在簧片的前表面和后表面上的激励电极。 激励电极中的一个通过穿过压电振动片的短边并且在压电振动片的一个短边附近的中心线上的金属凸块连接到基底基板。 另一个激励电极通过与上述短边相同侧的金属凸块连接到基底基板，并且在压电振动片的短边与压电振动片的较长侧的一侧相交的部分附近 芦苇。

公开(公告)号：US20110233694A1

公开(公告)日：2011-09-29

申请号：US13070995

申请日：2011-03-24

申请人： Yoshifumi Yoshida

发明人： Yoshifumi Yoshida

IPC分类号： H01L29/84 ,  H01L21/50

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/16152 ,  H03H9/1014 ,  H03H9/1071 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014

摘要： A manufacturing method of an electronic device package includes: forming concave portions that later form the cavities in one surface of a cover substrate; forming a first metal film on the cover substrate on a surface opposite to the surface in which the concave portions are formed; forming a second metal film on the cover substrate on the surface in which the concave portions are formed; bonding a base substrate and the cover substrate together via the second metal film. It thus becomes possible to provide an electronic device package in which the base substrate and the cover substrate are boned together via the metal film in a stable manner by minimizing warping of the substrate even when the substrate is made thinner.

摘要翻译： 电子器件封装的制造方法包括：形成稍后在覆盖基板的一个表面中形成空腔的凹部; 在与形成所述凹部的表面相反的表面上在所述盖基板上形成第一金属膜; 在形成有所述凹部的表面上的所述盖基板上形成第二金属膜; 通过第二金属膜将基底基板和盖基板接合在一起。 因此，即使在使基板变薄时，也可以通过使基板的翘曲最小化，以稳定的方式将基底基板和盖基板结合在一起，从而可以提供电子器件封装。

公开(公告)号：US08012835B2

公开(公告)日：2011-09-06

申请号：US12283639

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

摘要翻译： 高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。 源区域可操作以接收信号电位和信号电流中的至少一个。 半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。 栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。 栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。

公开(公告)号：US20110193643A1

公开(公告)日：2011-08-11

申请号：US13021408

申请日：2011-02-04

申请人： Yoshihisa Tange ,  Yoshifumi Yoshida

发明人： Yoshihisa Tange ,  Yoshifumi Yoshida

IPC分类号： H03B5/32 ,  H01L41/053 ,  H01L41/22

CPC分类号： H03H9/1021 ,  H01L21/4803 ,  H01L21/50 ,  H01L23/055 ,  H01L2924/0002 ,  Y10T29/42 ,  H01L2924/00

摘要： Provided is a method of manufacturing a package capable of providing a plurality of through-electrodes in a base substrate made of a glass material with high position precision. An electrode member having a plurality of pins erected on a base is prepared, the plurality of pins is inserted into a plurality of through-holes of a glass substrate provided with the plurality of through-holes, the resultant is heated to a temperature higher than the softening point of the glass substrate to weld the corresponding through-holes and the pins to each other, the glass substrate is ground after cooling to remove the base, and the pins are exposed from both surfaces of the glass substrate, thereby forming through-electrodes which are electrically separated from each other.

摘要翻译： 提供一种制造能够在具有高位置精度的由玻璃材料制成的基底基板中提供多个通孔的封装的方法。 准备具有竖立在基座上的多个销的电极构件，将多个销插入设置有多个通孔的玻璃基板的多个通孔中，将其加热至高于 玻璃基板的软化点将相应的通孔和销彼此焊接，玻璃基板在冷却后被研磨以去除基部，并且销从玻璃基板的两个表面露出， 彼此电分离的电极。

公开(公告)号：US20110193642A1

公开(公告)日：2011-08-11

申请号：US13020538

申请日：2011-02-03

申请人： Yoshihisa Tange ,  Yoshifumi Yoshida

发明人： Yoshihisa Tange ,  Yoshifumi Yoshida

IPC分类号： H03B5/32 ,  H03H9/17

CPC分类号： H03H9/0542 ,  H01L2224/16225 ,  H01L2924/16152 ,  H03H9/1021 ,  H03H9/17

摘要： In a piezoelectric vibrator in which a piezoelectric vibrating reed is mounted on a mounting portion installed on a surface of the base substrate in a cantilevered state and the piezoelectric vibrating reed is accommodated to be covered by a lid substrate, the resistance of a lead-out electrode for supplying a drive power to the piezoelectric vibrating reed is reduced, thereby preventing degradation of vibrating performance. A first lead-out electrode is formed between a first through-electrode and a mounting portion formed on a base substrate, a conductor film is formed from a bonding member on a bonding surface where the base substrate and a lid substrate are bonded to each other, the first lead-out electrode and the conductor film are electrically connected to each other via the first connection portion in the vicinity of the mounting portion and via the second connection portion in the vicinity of the first through-electrode, thereby reducing the resistance of the first lead-out electrode.

摘要翻译： 在将压电振动片安装在安装在基底基板的表面上的悬置状态的压电振动片的压电振动器中，并且压电振动片容纳被盖基板覆盖时，导出电阻 用于向压电振动片供给驱动力的电极减少，从而防止振动性能的劣化。 第一引出电极形成在第一贯通电极和形成在基底基板上的安装部之间，导体膜由基底基板和盖基板彼此接合的接合面上的接合部件形成 第一引出电极和导体膜经由第一连接部分在安装部分附近并且经由第二连接部分在第一贯通电极附近彼此电连接，由此降低电阻 第一个引出电极。

公开(公告)号：USRE42223E1

公开(公告)日：2011-03-15

申请号：US11391668

申请日：2006-03-28

申请人： Miwa Wake ,  Yoshifumi Yoshida

发明人： Miwa Wake ,  Yoshifumi Yoshida

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624

摘要： Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a LOCOS reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.

摘要翻译： 通常，当支撑基板的电位固定时，产生如下问题：即使在使用支撑基板的寄生晶体管的产生时，即使在漏极附近的嵌入绝缘膜附近也产生冲击离子，作为 门，以便可能引起寄生双极性操作。 本发明的方法包括以下步骤：形成和图案化到达嵌入式绝缘膜的LOCOS，栅极氧化膜，阱和用作栅电极的多晶硅膜; 在源极区域和漏极区域的每一个的超浅部分中形成第二导电型高密度杂质区域，在超导体的第二导电型高密度杂质区域处具有低密度的第二导电类型杂质区域 在第二导电型杂质区具有低密度且高于嵌入绝缘膜的第二导电型杂质区; 在所述栅电极周围形成侧壁; 在源极区域和漏极区域中形成第二导电型杂质区域; 形成层间绝缘膜，并在源极区，漏极区和栅电极中形成接触孔; 并在层间绝缘膜上形成布线。

公开(公告)号：US07816212B2

公开(公告)日：2010-10-19

申请号：US12283638

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L29/4238

摘要： A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

摘要翻译： 高电压工作场效应晶体管具有衬底和设置在衬底的表面中的半导体沟道形成区域。 源极区域和漏极区域彼此间隔开，半导体沟道形成区域设置在源极区域和漏极区域之间。 栅极绝缘膜区域设置在半导体沟道形成区域上。 电阻栅极区域设置在栅极绝缘膜区域上。 源极电极设置在电阻栅极区域的源极区域侧并且可操作以接收信号电位。 漏极侧电极设置在电阻栅极区域的漏极侧，并且可操作以接收其绝对值等于或大于指定电位的绝对值的偏置电位，并且其根据增加或 降低漏极电位。

公开(公告)号：US20070254426A1

公开(公告)日：2007-11-01

申请号：US11821977

申请日：2007-06-26

申请人： Miwa Wake ,  Yoshifumi Yoshida

发明人： Miwa Wake ,  Yoshifumi Yoshida

IPC分类号： H01L21/8238

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624

摘要： Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a LOCOS reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.

摘要翻译： 通常，当支撑基板的电位固定时，产生如下问题：即使在使用支撑基板的寄生晶体管的产生时，即使在漏极附近的嵌入绝缘膜附近也产生冲击离子，作为 门，以便可能引起寄生双极性操作。 本发明的方法包括以下步骤：形成和图案化到达嵌入式绝缘膜的LOCOS，栅极氧化膜，阱和用作栅电极的多晶硅膜; 在源极区域和漏极区域的每一个的超浅部分中形成第二导电型高密度杂质区域，在超导体的第二导电型高密度杂质区域处具有低密度的第二导电类型杂质区域 在第二导电型杂质区具有低密度且高于嵌入绝缘膜的第二导电型杂质区; 在所述栅电极周围形成侧壁; 在源极区域和漏极区域中形成第二导电型杂质区域; 形成层间绝缘膜，并在源极区，漏极区和栅电极中形成接触孔; 并在层间绝缘膜上形成布线。