公开(公告)号：US5750781A

公开(公告)日：1998-05-12

申请号：US485143

申请日：1995-06-07

申请人： Yoshifumi Yoshida ,  Akira Tanigawa ,  Satoshi Yamamoto

发明人： Yoshifumi Yoshida ,  Akira Tanigawa ,  Satoshi Yamamoto

IPC分类号： C08F2/10 ,  C08F20/52 ,  C08F26/02 ,  C08F220/56 ,  C08F226/04 ,  C07C231/12

CPC分类号： C08F220/56 ,  C08F226/04

摘要： A process for preparing an aqueous solution of an ionic copolymer having a copolymer concentration of 20 % by weight or less and a viscosity of 20 ps or more at 25.degree. C. which comprises conducting copolymerization of an acrylamide compound(B) with a diallylamine compound(A) by continuously adding an aqueous solution of (B) having a concentration of 30% by weight or less to an aqueous solution of the diallylamine compound(A) having a concentration of 5% by weight or more and less than 10% by weight, and this process exhibit high conversion of diallylamine compounds, of which reactivity is low, and a copolymer having a high molecular weight can be obtained.

摘要翻译： 一种在25℃下制备共聚物浓度为20重量％以下且粘度为20ps以上的离子共聚物的水溶液的方法，其包括使丙烯酰胺化合物（B）与二烯丙基胺化合物 （A）通过将浓度为30重量％以下的（B）的水溶液连续添加到浓度为5重量％以上且小于10体积％的二烯丙基胺化合物（A）的水溶液中，通过 重量，并且该方法表现出高反应性的二烯丙基胺化合物的高转化率，并且可以获得具有高分子量的共聚物。

公开(公告)号：US5521240A

公开(公告)日：1996-05-28

申请号：US473900

申请日：1995-06-07

申请人： Yoshifumi Yoshida ,  Toshiyuki Hasegawa ,  Akira Tanigawa ,  Fujiko Kumei ,  Akira Kawamura

发明人： Yoshifumi Yoshida ,  Toshiyuki Hasegawa ,  Akira Tanigawa ,  Fujiko Kumei ,  Akira Kawamura

IPC分类号： C09D179/00 ,  C08G12/00 ,  C08G73/00 ,  C08G73/02 ,  C09D179/02 ,  D21H19/00 ,  D21H19/44 ,  D21H19/62 ,  C08K5/20 ,  C08K5/315

CPC分类号： C09D179/02 ,  C08G12/00 ,  C08G73/022 ,  D21H19/62

摘要： A paper coating composition which comprises:(I) a pigment;(II) an aqueous binder;(III) a mixture or a reaction product ofa water-soluble resin (A) which can be obtained by reacting, at least, (a) an alkylenediamine or a polyalkylenepolyamine, (b) an urea compound and (c) a compound selected from aldehydes, epihalohydrins and .alpha.,.gamma.-dihalo-.beta.-hydrins; andan amide compound (B-1) which can be obtained by reacting (x) an .alpha.,.beta.-unsaturated carboxylic acid compound and (y) a primary or secondary amino compound, oran aminonitrile compound (B-2) which can be obtained by reacting (z) an .alpha.,.beta.-unsaturated nitryl compound and (y) a primary or secondary amino compound; wherein the water-soluble resin of the component (A) may be further allowed to react with a dibasic carboxylic compound, an alicyclic amine and/or an alicyclic epoxy compound in addition to the above three ingredients; andpaper coated by using the above composition is especially excellent in ink receptivity and water resistance.

摘要翻译： 一种纸涂料组合物，其包含：（I）颜料; （II）水性粘合剂; （III）可通过至少使（a）亚烷基二胺或聚亚烷基多胺反应获得的水溶性树脂（A）的混合物或反应产物，（b）脲化合物和（c）选择的化合物 来自醛，表卤代醇和α，γ-二卤代-β-氢化物; 和（x）α，β-不饱和羧酸化合物和（y）伯或仲氨基化合物或氨基腈化合物（B-2）可以得到的酰胺化合物（B-1） 通过使（z）α，β-不饱和硝基化合物和（y）伯或仲氨基化合物反应而获得; 其中除了上述三种成分之外，还可以使组分（A）的水溶性树脂与二元羧酸化合物，脂环族胺和/或脂环族环氧化合物反应; 并且通过使用上述组合物涂布的纸具有特别优异的耐油性和耐水性。

公开(公告)号：US20090295838A1

公开(公告)日：2009-12-03

申请号：US12453973

申请日：2009-05-28

申请人： Akira Tanigawa

发明人： Akira Tanigawa

IPC分类号： G09G5/10 ,  H03M1/76

CPC分类号： G09G3/3688 ,  G09G2310/027

摘要： A DA converter circuit configured to output a gray scale voltage to a liquid crystal display panel is disclosed, wherein the gray scale voltage is generated from reference voltages fewer than gray scales of the liquid crystal display panel and it is still to be able to prevent deterioration in display quality of the liquid crystal display panel. A DA converter circuit of at least one embodiment includes: a reference voltage generator circuit for generating reference voltages; a selector circuit for selecting one or two reference voltages from the reference voltages in according to the inputted gray scale value; and a voltage follower circuit for outputting the gray scale voltage that is the one reference voltage thus selected or a mean value of the two reference voltages thus selected. Reference voltages are generated, in at least one embodiment, as a variety of gray scale voltages.

摘要翻译： 公开了一种配置成将灰度电压输出到液晶显示面板的DA转换电路，其中灰度电压是由比液晶显示面板的灰度小的参考电压产生的，并且仍然能够防止劣化 在液晶显示面板的显示质量。 至少一个实施例的DA转换器电路包括：用于产生参考电压的参考电压发生器电路; 选择器电路，用于根据输入的灰度值从参考电压中选择一个或两个参考电压; 以及用于输出作为如此选择的一个参考电压的灰度级电压或由此选择的两个参考电压的平均值的电压跟随器电路。 在至少一个实施例中，产生参考电压作为各种灰度级电压。

公开(公告)号：US20100030943A1

公开(公告)日：2010-02-04

申请号：US10589375

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G11C7/1027 ,  G11C7/1072

摘要： A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal.

摘要翻译： 具有与时钟信号同步的突发模式读取功能的半导体存储器包括由多个存储器单元组成的存储器阵列，用于将接收到的地址的上部组释放为存储器访问地址的同步读取控制电路和下部组 的接收地址作为与时钟信号同步的突发地址;读出放大器，用于释放由存储器地址选择的每个存储器单元的输出数据，解码器，用于解码突发地址;地址锁存器，用于锁存解码的 突发地址与时钟信号同步，用于保存输出数据并选择由地址锁存器的突发地址确定的输出数据中的相应一个的页选择器，以及用于与时钟信号同步地锁存输出数据的输出锁存器 。

公开(公告)号：US20070279111A1

公开(公告)日：2007-12-06

申请号：US10589403

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A DLL circuit having a phase comparison circuit for comparing phases of a reference clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched at a logic “1” by start of 1 clock cycle of an internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting duration time of the logic “1” of the first signal input by the variable delay addition circuit through the dummy delay until the end of the 1 clock cycle of the internal clock and setting an initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 具有用于比较参考时钟和延迟时钟的相位的相位比较电路的DLL电路和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括用于输入锁存在逻辑上的第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的1个时钟周期开始到可变延迟加法电路的“1”和用于检测由可变延迟输入的第一信号的逻辑“1”的持续时间的装置 通过虚拟延迟的加法电路，直到内部时钟的1个时钟周期结束，并且基于持续时间设置可变延迟加法电路的延迟量的初始值。

公开(公告)号：US20070279113A1

公开(公告)日：2007-12-06

申请号：US10590225

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1534 ,  H03L7/0818

摘要： A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay amount according to a delay amount adjustment signal, and a phase comparison circuit comparing phases of the internal clock and a delay clock input via the variable delay addition circuit and the dummy delay and outputting the delay amount adjustment signal to the variable delay addition circuit. At the start of burst, a first signal set at a logic “1” during 1 clock cycle of the internal clock is input to the variable delay addition circuit via the dummy delay, and duration time of the logic “1” of the first signal is detected until 1 clock cycle of the internal clock is completed and delay amount of the variable delay addition circuit is initialized by setting one of the coarse delay circuit based on the duration time.

摘要翻译： DLL电路包括对应于来自外部时钟的内部时钟延迟的虚拟延迟，具有根据延迟量调整信号调整延迟量的粗略和精细延迟电路的可变延迟加法电路，以及相位比较电路， 内部时钟和通过可变延迟加法电路输入的延迟时钟和虚拟延迟，并将延迟量调整信号输出到可变延迟加法电路。 在突发开始时，在内部时钟的1个时钟周期期间被设置为逻辑“1”的第一信号经由虚拟延迟被输入到可变延迟加法电路，并且第一信号的逻辑“1”的持续时间 被检测到内部时钟的1个时钟周期完成，并且通过基于持续时间设置粗略延迟电路之一来初始化可变延迟加法电路的延迟量。

公开(公告)号：US20070279112A1

公开(公告)日：2007-12-06

申请号：US10589428

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic “1” by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic “1” of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 使用具有用于比较内部时钟和延迟时钟的相位的相位比较电路的DLL电路的半导体存储器和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括：用于输入第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的一个时钟周期的开始锁存到逻辑“1”，并通过第一信号的逻辑“1”的持续时间检测装置 通过可变延迟加法电路通过虚拟延迟输入，直到内部时钟的一个时钟周期完成，并根据持续时间设定可变延迟加法电路的延迟量的初始值。