公开(公告)号：US10483369B2

公开(公告)日：2019-11-19

申请号：US15797723

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Jinsheng Gao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10461155B2

公开(公告)日：2019-10-29

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US10446683B2

公开(公告)日：2019-10-15

申请号：US15702278

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Hong Yu

IPC: H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed.

公开(公告)号：US10446483B2

公开(公告)日：2019-10-15

申请号：US15872589

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US10439026B2

公开(公告)日：2019-10-08

申请号：US15786284

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu Wong ,  Hui Zang ,  Xusheng Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US10347729B2

公开(公告)日：2019-07-09

申请号：US15590459

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40

Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US10224418B2

公开(公告)日：2019-03-05

申请号：US15793419

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L23/48 ,  H01L29/66 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L29/78 ,  H01L29/207 ,  H01L21/311

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US10204991B2

公开(公告)日：2019-02-12

申请号：US15482086

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu ,  Min-hwa Chi

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/732

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US10176995B1

公开(公告)日：2019-01-08

申请号：US15673232

申请日：2017-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Haigou Huang

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L21/28 ,  H01L29/66

Abstract: At least one method, apparatus and system disclosed herein involves a gate cut process using a stress material for a finFET device. A set of fins are formed on a semiconductor substrate. A gate region is formed above a portion of the set of fins. A gate cut trench is formed within the gate region. A dielectric material comprising an intrinsic stress is deposited into the gate cut region. A replacement metal gate process is performed in the gate region. Residue metal features are removed about the gate cut region.