公开(公告)号：US20160118499A1

公开(公告)日：2016-04-28

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。

公开(公告)号：US20150357433A1

公开(公告)日：2015-12-10

申请号：US14299829

申请日：2014-06-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/266

CPC classification number: H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/78

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an implant mask overlying a dummy gate, where the implant mask produces a masked dummy gate and an exposed dummy gate. Ions are implanted into the exposed dummy gate, and the implant mask is removed. The masked dummy gate is etched with an etchant selective to the masked dummy gate over the exposed dummy gate to form a trench, and the trench is filled with a conductive material.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成覆盖在虚拟栅极上的注入掩模，其中所述注入掩模产生掩蔽的伪栅极和暴露的伪栅极。 将离子注入暴露的虚拟栅极中，并移除植入物掩模。 用掩蔽的伪栅极对暴露的伪栅极选择性地蚀刻掩蔽的虚拟栅极以形成沟槽，并且沟槽填充有导电材料。

公开(公告)号：US20140154854A1

公开(公告)日：2014-06-05

申请号：US14027837

申请日：2013-09-16

Applicant: Globalfoundries, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。

公开(公告)号：US08716126B2

公开(公告)日：2014-05-06

申请号：US13769446

申请日：2013-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

IPC: H01L21/4763

CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。

公开(公告)号：US10707330B2

公开(公告)日：2020-07-07

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L21/285 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

公开(公告)号：US10522655B2

公开(公告)日：2019-12-31

申请号：US15711674

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20190043963A1

公开(公告)日：2019-02-07

申请号：US15667755

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees ,  Clemens Fitz

IPC: H01L29/66 ,  H01L29/417

Abstract: A transistor element of a sophisticated semiconductor device includes a gate electrode structure including a metal-containing electrode material instead of the conventionally used highly doped semiconductor material. The metal-containing electrode material may be formed in an early manufacturing stage, thereby reducing overall complexity of patterning the gate electrode structure in approaches in which the gate electrode structure is formed prior to the formation of the drain and source regions. Due to the metal-containing electrode material, high conductivity at reduced parasitic capacitance may be achieved, thereby rendering the techniques of the present disclosure as highly suitable for further device scaling.

公开(公告)号：US10103067B1

公开(公告)日：2018-10-16

申请号：US15617388

申请日：2017-06-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Gunter Grasshoff ,  Rico Hueselitz

IPC: H01L21/76 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L21/8238

Abstract: A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.

公开(公告)号：US20180047642A1

公开(公告)日：2018-02-15

申请号：US15232090

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/84 ,  H01L21/265 ,  H01L27/12 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/7834

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

公开(公告)号：US09608003B2

公开(公告)日：2017-03-28

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/308 ,  H01L21/321 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.