公开(公告)号：US09324722B1

公开(公告)日：2016-04-26

申请号：US14797757

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Lei Yuan ,  Jongwook Kye

IPC: H01L21/4763 ,  H01L27/11 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.

Abstract translation: 公开了一种利用切割掩模结合块掩模在IC器件中形成金属布线的方法。 实施例包括在氧化硅层的上表面上形成硬掩模层; 在所述硬掩模的上表面上形成间隔开的平行心轴; 在每个心轴的相对侧上形成间隔物，去除心轴，形成交替的心轴和非心轴空间; 在心轴和非心轴空间上形成阻挡掩模部分; 去除所述氧化硅的所述硬掩模暴露部分的暴露部分，去除所述阻挡掩模部分; 在所述硬掩模的上表面上形成具有比所述阻挡掩模部分更短的开口的切割掩模; 通过切割掩模开口去除硬掩模，去除切割掩模; 在氧化硅的暴露区域中形成空腔; 去除间隔物和任何剩余的硬掩模; 并在空腔中形成金属线。

公开(公告)号：US20160049481A1

公开(公告)日：2016-02-18

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US20150287636A1

公开(公告)日：2015-10-08

申请号：US14246476

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US20150286764A1

公开(公告)日：2015-10-08

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing e overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将第一和第二金属特征的e整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US20150113484A1

公开(公告)日：2015-04-23

申请号：US14578717

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

Abstract translation: 本文公开的一种方法尤其涉及生成一组心轴掩模规则，块掩模规则和基于软件的虚拟金属掩模。 该方法还包括创建一组虚拟非心轴掩模规则，该规则是心轴掩模规则的副本，基于心轴掩模规则，块掩模规则和虚拟非心轴掩模生成一组金属路由设计规则 规则，基于金属路由设计规则生成电路布线布局，将电路路由布局分解为心轴掩模图案和块掩模图案，产生对应于心​​轴掩模图案的第一组掩模数据，以及生成第二组 对应于块掩模图案的掩模数据。

公开(公告)号：US08921225B2

公开(公告)日：2014-12-30

申请号：US13766141

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry Levinson

IPC: H01L21/308 ,  H01L21/28 ,  H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。

公开(公告)号：US20140327153A1

公开(公告)日：2014-11-06

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。

公开(公告)号：US08881083B1

公开(公告)日：2014-11-04

申请号：US13874803

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US20140273474A1

公开(公告)日：2014-09-18

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Youngtag WOO ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。