公开(公告)号：US06963501B2

公开(公告)日：2005-11-08

申请号：US10799776

申请日：2004-03-15

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/02 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3454

Abstract: An aspect of the present invention provides a nonvolatile memory that includes a memory cell array including a data storage area to store a data, and a data invert flag storage area to store a data invert flag indicating whether or not the data is inverted. The memory cell array outputs selected data and a data invert flag related to the selected data. A state machine determines whether or not the number of memory cells to which a bias voltage is applied is equal to or greater than a predetermined number when writing data into the memory cell array. The state machine instructs a data controller to transfer inverted data and a data invert flag if it is equal to or greater than the predetermined number.

Abstract translation: 本发明的一个方面提供一种包括存储单元阵列的非易失性存储器，该存储单元阵列包括用于存储数据的数据存储区域和数据反转标志存储区域，以存储指示数据是否反转的数据反转标志。 存储单元阵列输出所选择的数据和与所选数据相关的数据反相标志。 当将数据写入存储单元阵列时，状态机确定施加偏置电压的存储单元的数量是否等于或大于预定数。 如果状态机等于或大于预定数量，则状态机指示数据控制器传送反转数据和数据反转标志。

公开(公告)号：US06937524B2

公开(公告)日：2005-08-30

申请号：US10461995

申请日：2003-06-11

Applicant: Hitoshi Shiga ,  Naoya Tokiwa

Inventor： Hitoshi Shiga ,  Naoya Tokiwa

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C2216/14

Abstract: A non-volatile semiconductor memory device capable of performing page programming at high speeds is provided. This nonvolatile memory device includes a cell array with a matrix of rows and columns of electrically writable and erasable nonvolatile memory cells, and a write control circuit which writes or “programs” one-page data into this cell array at a plurality of addresses within one page. The write control circuit is operable to iteratively perform iteration of a write operation for the plurality of addresses corresponding to one page and iteration of a verify-read operation of the plurality of addresses after writing until verify-read check is passed with respect to every address involved. Regarding an address or addresses with no cells to be written any more, the write control circuit skips the write operation and the after-write verify-read operation.

Abstract translation: 提供能够高速执行页面编程的非易失性半导体存储器件。 这种非易失性存储器件包括具有电可写和可擦除非易失性存储单元的行和列的矩阵的单元阵列，以及一个写入控制电路，其在一个位置内的多个地址中将一页数据写入或“编程”到该单元阵列 页。 写入控制电路可操作以迭代地执行对应于一页的多个地址的写入操作和写入之后多个地址的验证读取操作的迭代，直到相对于每个地址通过验证读取检查 涉及。 关于不再写入单元的地址或地址，写入控制电路跳过写入操作和写入后验证读取操作。

公开(公告)号：US06928002B2

公开(公告)日：2005-08-09

申请号：US10884739

申请日：2004-07-01

Applicant: Hitoshi Shiga ,  Tokumasa Hara ,  Tadayuki Taura

Inventor： Hitoshi Shiga ,  Tokumasa Hara ,  Tadayuki Taura

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/107 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.

Abstract translation: 一种非易失性半导体存储器件包括多个块，每个块具有一次要擦除的多个存储器单元和用于选择存储器单元的解码器，每个块具有块解码器，用于将其选择信号锁存在预先 编程并用于同时通过选择信号选择所有锁存块，读出放大器和用于控制序列的地址控制电路，该序列包括擦除和擦除所有所选择的所有存储单元的计数地址 预编程后的存储单元，具有锁存选择信号的所有块被控制为由地址控制电路共同擦除。

公开(公告)号：US06903983B2

公开(公告)日：2005-06-07

申请号：US10325753

申请日：2002-12-23

Applicant: Tokumasa Hara ,  Hidetoshi Saito ,  Hitoshi Shiga ,  Yasuhiko Honda ,  Tadayuki Taura ,  Hideo Kato

Inventor： Tokumasa Hara ,  Hidetoshi Saito ,  Hitoshi Shiga ,  Yasuhiko Honda ,  Tadayuki Taura ,  Hideo Kato

IPC: G11C16/02 ,  G11C8/18 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C8/18 ,  G11C16/32 ,  G11C2216/22

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

Abstract translation: 半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号 生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。 读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。

公开(公告)号：US20050078519A1

公开(公告)日：2005-04-14

申请号：US10799776

申请日：2004-03-15

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/02 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3454

Abstract: An aspect of the present invention provides a nonvolatile memory that includes a memory cell array including a data storage area to store a data, and a data invert flag storage area to store a data invert flag indicating whether or not the data is inverted. The memory cell array outputs selected data and a data invert flag related to the selected data. A state machine determines whether or not the number of memory cells to which a bias voltage is applied is equal to or greater than a predetermined number when writing data into the memory cell array. The state machine instructs a data controller to transfer inverted data and a data invert flag if it is equal to or greater than the predetermined number.

公开(公告)号：US06590813B2

公开(公告)日：2003-07-08

申请号：US10180076

申请日：2002-06-27

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C1604

CPC classification number: G11C16/3445 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3459

Abstract: A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.

公开(公告)号：US06552936B2

公开(公告)日：2003-04-22

申请号：US10052303

申请日：2002-01-18

Applicant: Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC: G11C1604

CPC classification number: G11C7/1021 ,  G11C8/10

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.