公开(公告)号：US06309555B1

公开(公告)日：2001-10-30

申请号：US09260202

申请日：1999-03-01

申请人： Hsueh-Chung Chen

发明人： Hsueh-Chung Chen

IPC分类号： B44C122

CPC分类号： B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  G01B11/0683 ,  G01N17/00 ,  H01L21/31053

摘要： A method for real-time detecting the thickness of a material layer. A reflected light is measured of an incident light emitted toward the material layer. By integrating the intensity of the reflected light along the time axis, followed by dividing by the product of the derivative of the intensity of the reflected light and the polishing time, an I-Dt transformation curve can be obtained. Since the I-Dt transformation curve has characteristics associated with a cosecant function, which has salient peaks on the curve, the thickness of the material layer can be real-time determined. Furthermore, due to the facts that the transformed curve has salient peaks, the function itself reveals the sign of the slope, and the transformed curve are relatively flat between peaks, correct and stable rules can therefore be provided to determine the analytical endpoint.

摘要翻译： 一种用于实时检测材料层厚度的方法。 测量朝向材料层发射的入射光的反射光。 通过将反射光的强度沿着时间轴积分，然后除以反射光强度的导数与抛光时间的乘积，可以得到I-Dt变换曲线。 由于I-Dt变换曲线具有与曲线上具有突出峰值的辅助功能相关联的特征，因此材料层的厚度可以被实时确定。 此外，由于转换曲线具有突出峰值的事实，该函数本身揭示了斜率的符号，并且变换曲线在峰之间相对平坦，因此可以提供正确和稳定的规则来确定分析端点。

公开(公告)号：US06303461B1

公开(公告)日：2001-10-16

申请号：US09221203

申请日：1998-12-23

申请人： Hsueh-Chung Chen ,  Chien-Hung Chen

发明人： Hsueh-Chung Chen ,  Chien-Hung Chen

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method for fabricating a shallow trench isolation (STI) structure is provided. The method contain sequentially forming a pad oxide layer, a hard layer, and a polysilicon layer on the substrate, all of which are patterned to form a trench in the substrate to define several active areas. The hard layer usually includes silicon nitride. An insulating layer is formed over the substrate so that the trench is also filled. A CMP process is performed to polish the insulating layer. The CMP process is continuously performed until the hard layer is completely exposed. The hard layer and the pad oxide layer are sequentially removed to form the STI structure.

摘要翻译： 提供了一种制造浅沟槽隔离（STI）结构的方法。 该方法包括在衬底上顺序地形成衬垫氧化物层，硬质层和多晶硅层，所有这些都被图案化以在衬底中形成沟槽以限定若干有效区域。 硬层通常包括氮化硅。 在衬底上形成绝缘层，使得沟槽也被填充。 执行CMP工艺以抛光绝缘层。 连续进行CMP工艺，直到硬质层完全暴露。 顺序地除去硬质层和焊盘氧化物层以形成STI结构。

公开(公告)号：US6048794A

公开(公告)日：2000-04-11

申请号：US954048

申请日：1997-10-20

申请人： Hsueh-Chung Chen ,  Chine-Gie Lou

发明人： Hsueh-Chung Chen ,  Chine-Gie Lou

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76879

摘要： The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.

摘要翻译： 本发明提供一种使用具有自对准的W-硅化物阻挡层34的选择性W CVD工艺制造与衬底接触的钨（W）插头36的方法。该方法包括以下步骤：将第一绝缘层20形成在 硅半导体衬底10; 在第一绝缘层20中形成暴露基板表面的第一（接触）开口24; 在暴露的衬底表面上选择性地生长薄的第一钨层30; 从薄的第一钨层30快速热退火形成薄的第一硅化钨层34; 在基本上填充第一开口36的第一薄钨硅酸盐层34上选择性地沉积钨塞36，从而形成W插头接触。 RTA / W硅化物层34降低了接触电阻，增加了粘附性，并且有助于W插塞36的选择性沉积。

公开(公告)号：US6024628A

公开(公告)日：2000-02-15

申请号：US235690

申请日：1999-01-22

申请人： Hsueh-Chung Chen

发明人： Hsueh-Chung Chen

IPC分类号： B24B37/04 ,  B24B49/04 ,  B24B49/12 ,  B24B49/00 ,  B24B51/00

CPC分类号： B24B37/005 ,  B24B37/042 ,  B24B49/04 ,  B24B49/12

摘要： A method of determining a real time removal rate. A material layer is polished. During the polishing process, a light is incident onto the material layer continuously. The incident light is reflected from the material layer with a reflected light intensity. By integrating the reflected light intensity, followed by dividing the integration with a product of a differential of the reflected light intensity and the polishing time, an I-Dt transformation is obtained. The I-Dt transformation has a period which reflects the removal rate through calculation of optical principle.

摘要翻译： 一种确定实时清除率的方法。 材料层被抛光。 在抛光过程中，光线连续地入射到材料层上。 入射光以反射光强度从材料层反射。 通过积分反射光强度，然后将积分与反射光强度和抛光时间的微分积积分，得到I-Dt变换。 I-Dt变换具有通过计算光学原理反映去除率的时间段。

公开(公告)号：US20130082333A1

公开(公告)日：2013-04-04

申请号：US13610385

申请日：2012-09-11

申请人： Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

发明人： Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

IPC分类号： H01L27/088

CPC分类号： H01L21/823431 ,  H01L27/0886

摘要： Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position.

公开(公告)号：US20120098133A1

公开(公告)日：2012-04-26

申请号：US12910075

申请日：2010-10-22

申请人： CHIH-CHAO YANG ,  Hsueh-Chung Chen

发明人： CHIH-CHAO YANG ,  Hsueh-Chung Chen

IPC分类号： H01L23/482 ,  H01L21/31 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L21/321 ,  H01L21/02304 ,  H01L21/76852 ,  H01L21/76886

摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.

摘要翻译： 可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。 根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。

公开(公告)号：US20060199381A1

公开(公告)日：2006-09-07

申请号：US11306193

申请日：2005-12-19

申请人： Hsueh-Chung Chen ,  Teng-Chun Tsai ,  Ming-Sheng Yang

发明人： Hsueh-Chung Chen ,  Teng-Chun Tsai ,  Ming-Sheng Yang

IPC分类号： H01L21/4763

CPC分类号： C25D21/10 ,  C25D5/04 ,  C25D17/001 ,  H01L21/2885

摘要： An improved electro-chemical deposition copper (ECD-Cu) apparatus and a method of preventing cavities in an ECD-Cu thin film are provided. The electro-chemical deposition apparatus has a bath tank, an anode positioned in the bath tank, and a spin plate for positioning a semiconductor wafer that is used as a cathode. The method, by alternating a spin direction of the spin plate between a clockwise direction and a counterclockwise direction, every 1 to 10 seconds, prevents an electrolyte solution of the bath tank from forming a stable vortex, and suppresses a phenomenon of forming cavities in the ECD-Cu thin film when bubbles of the vortex adhere to the wafer surface.

摘要翻译： 提供改进的电化学沉积铜（ECD-Cu）装置和防止ECD-Cu薄膜中的空穴的方法。 电化学沉积装置具有浴缸，位于浴槽中的阳极和用作定位用作阴极的半导体晶片的旋转板。 该方法通过使旋转板的旋转方向在顺时针方向和逆时针方向之间每1〜10秒交替，防止浴槽的电解液形成稳定的涡流，并且抑制在该槽中形成空腔的现象 ECD-Cu薄膜当漩涡气泡粘附到晶片表面时。

公开(公告)号：US20060019414A1

公开(公告)日：2006-01-26

申请号：US10899252

申请日：2004-07-26

申请人： Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

发明人： Chien-Jung Wang ,  Su-Chen Fan ,  Ding-Da Hu ,  Hsueh-Chung Chen

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  G01R31/2853 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

摘要翻译： 描述了具有改善的抗空隙形成的布线结构及其制造方法。 布线结构具有包括大面积部分的第一导电层，该区域部分连接到具有多个“n”个重叠部分和至少一个弯曲部分的突起的端部。 突起的另一端连接到具有覆盖的第二导电层的通路的底部。 通过以45°和135°之间的角度重叠两个相邻段的端部形成弯曲。 突出部还可以包括在弯曲部以外的段端部处的至少一个延伸部。 弯曲部分和延伸部用作延迟空位从大面积部分扩散到通孔附近的瓶颈，并且对于铜互连或通孔测试结构尤其有效。

公开(公告)号：US06709544B2

公开(公告)日：2004-03-23

申请号：US10064526

申请日：2002-07-24

申请人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

发明人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

IPC分类号： B24B700

CPC分类号： B24B37/20 ,  B24B37/042

摘要： The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.

摘要翻译： 本发明涉及与现有制造工艺兼容的CMP设备。 本发明的CMP设备采用可以比晶片尺寸小的带状抛光压板，使得布局紧凑并且有效地利用空间，导致高产量和高效的生产管理。 本发明提供一种CMP设备，其通过选择各种抛光垫和/或抛光浆料，为不同的制造工艺执行CMP提供更大的灵活性。

公开(公告)号：US06638391B1

公开(公告)日：2003-10-28

申请号：US10177306

申请日：2002-06-19

申请人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L21302

CPC分类号： B24B37/30

摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

摘要翻译： 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。