公开(公告)号：US20180254332A1

公开(公告)日：2018-09-06

申请号：US15755448

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7851

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.

公开(公告)号：US20180130801A1

公开(公告)日：2018-05-10

申请号：US15577734

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US20170323955A1

公开(公告)日：2017-11-09

申请号：US15528743

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Glenn A. Glass

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/04 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L27/108 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

Abstract: An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.

公开(公告)号：US20170278964A1

公开(公告)日：2017-09-28

申请号：US15504171

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/423 ,  H01L29/201

CPC classification number: H01L29/7827 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/201 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/785 ,  H01L29/78696

Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

公开(公告)号：US20170278944A1

公开(公告)日：2017-09-28

申请号：US15503989

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/772 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L29/66469 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851

Abstract: Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped sub-structure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

公开(公告)号：US20160293760A1

公开(公告)日：2016-10-06

申请号：US15036571

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Chandra S. Mohapatra

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.

Abstract translation: 公开了一种用于形成这种器件的n-MOS晶体管器件和方法。 n-MOS晶体管器件包括在衬底上形成有一个或多个替换有源区的半导体衬底。 替代的有源区域包括第一III-V族半导体材料。 在替换有源区上方形成栅极结构。 源极/漏极（S / D）凹槽形成在与栅极结构相邻的替换有源区中。 替换S / D区域形成在S / D凹部中，并且包括具有小于第一III-V半导体材料的晶格常数的晶格常数的第二III-V半导体材料。 第二III-V材料的较小晶格常数在由第一III-V材料形成的沟道上引起单轴应变。 通道中的单轴应变改善了n-MOS器件中的载流子迁移率。