公开(公告)号：US20220384389A1

公开(公告)日：2022-12-01

申请号：US17885048

申请日：2022-08-10

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/544

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US11450560B2

公开(公告)日：2022-09-20

申请号：US16140398

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L21/768

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US11348897B2

公开(公告)日：2022-05-31

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan ,  Patrick Morrow ,  Kimin Jun ,  Brennen Mueller ,  Paul B. Fischer

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20220165686A1

公开(公告)日：2022-05-26

申请号：US17669265

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Kyle Yazzie ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H05K3/10 ,  B29C70/68 ,  H01L21/48 ,  H01L23/544 ,  H01L23/58

Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

公开(公告)号：US11322455B2

公开(公告)日：2022-05-03

申请号：US15845990

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Kyle Yazzie ,  Shawna M. Liff

IPC: H01L23/498 ,  H01L23/00 ,  H05K3/10 ,  B29C70/68 ,  H01L21/48 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  B29L31/34 ,  B29K63/00

Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

公开(公告)号：US11296052B2

公开(公告)日：2022-04-05

申请号：US16639085

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Preston T. Meyers ,  Javier A. Falcon ,  Shawna M. Liff ,  Joe R. Saucedo ,  Adel A. Elsherbini ,  Albert S. Lopez ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L25/00

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.

公开(公告)号：US20220102305A1

公开(公告)日：2022-03-31

申请号：US17032469

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US20220093725A1

公开(公告)日：2022-03-24

申请号：US17025209

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L49/02 ,  H01L23/49 ,  H01L23/492

Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US20220093492A1

公开(公告)日：2022-03-24

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H05K1/11 ,  H01L23/538 ,  H01L23/532

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.