中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

156 records (took 0.081 seconds)

    SELF-ALIGNED TOP VIA
    61.
    发明申请
    SELF-ALIGNED TOP VIA 有权

    公开(公告)号：US20210151377A1

    公开(公告)日：2021-05-20

    申请号：US16685192

    申请日：2019-11-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

    IPC: H01L23/538 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/762

    Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

    Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch
    62.
    发明授权
    Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch 有权

    公开(公告)号：US11004737B2

    公开(公告)日：2021-05-11

    申请号：US16433721

    申请日：2019-06-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Chi-Chun Liu ,  Peng Xu

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417

    Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

    SOURCE/DRAIN EXTENSION REGIONS AND AIR SPACERS FOR NANOSHEET FIELD-EFFECT TRANSISTOR STRUCTURES
    64.
    发明申请
    SOURCE/DRAIN EXTENSION REGIONS AND AIR SPACERS FOR NANOSHEET FIELD-EFFECT TRANSISTOR STRUCTURES 审中-公开

    公开(公告)号：US20200286992A1

    公开(公告)日：2020-09-10

    申请号：US16291443

    申请日：2019-03-04

    Applicant: International Business Machines Corporation

    Inventor： Yi Song ,  Zhenxing Bi ,  Kangguo Cheng ,  Chi-Chun Liu

    IPC: H01L29/08 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/324 ,  H01L21/764 ,  H01L27/088 ,  H01L29/10

    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

    Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch
    65.
    发明授权
    Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch 有权

    公开(公告)号：US10755976B2

    公开(公告)日：2020-08-25

    申请号：US16433627

    申请日：2019-06-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Chi-Chun Liu ,  Peng Xu

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/417

    Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

    Chip security fingerprint
    68.
    发明授权
    Chip security fingerprint 有权

    公开(公告)号：US10559542B2

    公开(公告)日：2020-02-11

    申请号：US15920562

    申请日：2018-03-14

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Shawn P. Fetterolf ,  Chi-Chun Liu

    IPC: H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  B81C1/00 ,  H01L21/033 ,  B82Y30/00

    Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

    FIELD EFFECT DEVICE WITH REDUCED CAPACITANCE AND RESISTANCE IN SOURCE/DRAIN CONTACTS AT REDUCED GATE PITCH
    70.
    发明申请
    FIELD EFFECT DEVICE WITH REDUCED CAPACITANCE AND RESISTANCE IN SOURCE/DRAIN CONTACTS AT REDUCED GATE PITCH 审中-公开

    公开(公告)号：US20190311949A1

    公开(公告)日：2019-10-10

    申请号：US16433627

    申请日：2019-06-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Chi-Chun Liu ,  Peng Xu

    IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/417

    Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

Patent Agency Ranking