公开(公告)号：US20240057345A1

公开(公告)日：2024-02-15

申请号：US17884002

申请日：2022-08-09

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Brent A. Anderson ,  Michael Rizzolo ,  Lawrence A. Clevenger

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

公开(公告)号：US11869783B2

公开(公告)日：2024-01-09

申请号：US17244084

申请日：2021-04-29

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert ,  James Stathis

IPC: H01L21/67 ,  G06N5/04 ,  G06N20/00

CPC classification number: H01L21/67271 ,  G06N5/04 ,  G06N20/00

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

公开(公告)号：US20230189655A1

公开(公告)日：2023-06-15

申请号：US17548828

申请日：2021-12-13

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Lisamarie White ,  Willie Lester Muchrison, JR. ,  Scott A. DeVries ,  Daniel Charles Edelstein ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.

公开(公告)号：US20230178474A1

公开(公告)日：2023-06-08

申请号：US17543964

申请日：2021-12-07

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H01L21/76807 ,  H01L21/32139 ,  H01L21/31144

Abstract: Semiconductor devices including a super via connection between levels are provided. The semiconductor device can include a first interlevel dielectric layer, a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer, a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer, a third interlevel dielectric layer disposed on the second interlevel dielectric layer, and a super via disposed on a second portion of the first interlevel dielectric layer, wherein a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer.

公开(公告)号：US20230086181A1

公开(公告)日：2023-03-23

申请号：US17483755

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Dimitri Houssameddine ,  Ruilong Xie ,  Kangguo Cheng ,  Michael Rizzolo

IPC: G11C11/16 ,  G11C11/18 ,  H01L43/08 ,  H01L43/04 ,  H01L43/10 ,  H01L43/14 ,  H01L27/22 ,  H01F10/32

Abstract: A cross-point SOT-MRAM cell includes: a first SHE write line; a second SHE write line non-colinear to the first SHE write line; a cross-point free layer comprising a first free layer, a second free layer, and a dielectric layer disposed between the first and the second free layers, the cross-point free layer configured to store a magnetic bit and located between and in contact with both the first SHE write line and the second SHE write line; and a remote sensing MTJ located in a vicinity of the cross-point free layer, wherein a free layer sensor of the remote sensing MTJ is in contact with one of the first SHE write line and the second SHE write line.

公开(公告)号：US20230006131A1

公开(公告)日：2023-01-05

申请号：US17943974

申请日：2022-09-13

Applicant: International Business Machines Corporation

Inventor： Kisup Chung ,  Michael Rizzolo ,  Fee Li Lie

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

公开(公告)号：US11444029B2

公开(公告)日：2022-09-13

申请号：US16799048

申请日：2020-02-24

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Nicholas Anthony Lanzillo ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/768

Abstract: A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.

公开(公告)号：US11424403B2

公开(公告)日：2022-08-23

申请号：US16797474

申请日：2020-02-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Bruce B. Doris ,  Michael Rizzolo ,  Alexander Reznicek

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: A method of fabricating an MRAM device, the method including forming a magnetoresistive random-access memory (MRAM) stack comprising a first hard mask, forming sidewall spacers adjacent to the MRAM stack, forming a layer of interconnect metal around and above the MRAM stack, recessing the interconnect metal, forming a layer of a second hard mask over the interconnect metal, and patterning and etching the second hard mask and interconnect metal, forming interconnect metal lines.

公开(公告)号：US11351811B2

公开(公告)日：2022-06-07

申请号：US16888126

申请日：2020-05-29

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Marc A. Bergendahl ,  Christopher J. Waskiewicz ,  Christopher J. Penny

IPC: G06K19/06 ,  B42D25/369 ,  G06K19/18 ,  G06K19/12 ,  B42D25/373 ,  G06F21/44 ,  B42D25/333 ,  G06F21/12

Abstract: An article is authenticated by providing a magnetic security mark in the form of an optically-passive randomly-generated nanoscale magnetic pattern. The pattern is pre-imaged and this reference image is uploaded to a secure database along with an identifier for the article such as a serial number. A user of the article verifies its authenticity by scanning it magnetically to obtain a scanned image of the magnetic pattern. The serial number is used to retrieve the previously uploaded reference image which is compared to the scanned image. If the images match, the article's authenticity is confirmed. A single article may have multiple magnetic security marks, each unique, placed at predetermined, non-uniform locations. The magnetic patterns are generated using thin film deposition of yttrium iron garnet. In one embodiment the article is a physical key having additional security features, such as mechanical features and a radio-frequency identification chip.

公开(公告)号：US11164377B2

公开(公告)日：2021-11-02

申请号：US15982710

申请日：2018-05-17

Applicant: International Business Machines Corporation

Inventor： Aldis Sipolins ,  Lawrence A. Clevenger ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Christopher J. Penny ,  Patrick Watson

IPC: G06F3/048 ,  G06T19/00 ,  G06F3/0481 ,  A63F13/245 ,  A63F13/211

Abstract: Methods and systems of navigating within a virtual environment are described. In an example, a processor may generate a portal that includes a set of portal boundaries. The processor may display the portal within a first scene of the virtual environment being displayed on a device. The processor may display a second scene of the virtual environment within the portal boundaries. The processor may receive sensor data indicating a movement of a motion controller. The processor may reposition the portal and the second scene in the first scene based on the sensor data, wherein the first scene remains stationary on the device during the reposition of the portal and the second scene. The processor may translate a location of the portal within the first scene to move the portal towards a user of the device until the second scene replaces the first scene being displayed on the device.