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    CMOS protection during germanium photodetector processing
    66.
    发明授权
    CMOS protection during germanium photodetector processing 有权
    锗光电探测器处理期间的CMOS保护

    公开(公告)号：US09590001B2

    公开(公告)日：2017-03-07

    申请号：US14732835

    申请日：2015-06-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Solomon Assefa ,  Marwan H. Khater ,  Edward W. Kiewra ,  Carol Reinholm ,  Steven M. Shank

    IPC: H01L27/146 ,  H01L27/144 ,  H01L31/028

    CPC classification number: H01L27/14607 ,  H01L27/1443 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/028

    Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

    Abstract translation: 提供了保护集成光子半导体结构内的CMOS器件的方法。 该方法可以包括在CMOS器件上沉积锗的保形层和与CMOS器件相邻的区域，在锗上沉积介电硬掩模的保形层，以及使用掩模级形成图案化的光致抗蚀剂层，以覆盖 CMOS器件和邻近区域内的光子器件形成区域。 将开口蚀刻到未被图案化光致抗蚀剂覆盖的氮化硅的沉积层的区域中，使得该区域与光子器件形成区域相邻。 然后在锗的共形层上蚀刻锗材料，其位于蚀刻开口下方的位置处，以在光子器件形成区域处形成光子器件。 沉积在CMOS器件上的锗的保形层保护CMOS器件。

    BACKSIDE CONTACT TO FINAL SUBSTRATE
    68.
    发明申请
    BACKSIDE CONTACT TO FINAL SUBSTRATE 有权
    背面接触到最终基底

    公开(公告)号：US20160372372A1

    公开(公告)日：2016-12-22

    申请号：US14744681

    申请日：2015-06-19

    Applicant: International Business Machines Corporation

    Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L21/768 ,  H01L23/482 ,  H01L23/48

    CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

    Abstract: Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

    Abstract translation: 用于与最终衬底的背面接触的器件结构和制造方法形成延伸穿过绝缘体上硅衬底的器件层并且部分地穿过绝缘体上硅衬底的掩埋绝缘体层的导电连接。 在形成导电连接之后，去除绝缘体上硅衬底的处理晶片。 在移除手柄晶片之后，部分去除掩埋绝缘体层以露出导电连接。 在埋入绝缘体层被部分去除之后，最后的衬底被耦合到埋入绝缘体层，使得导电连接与最终衬底耦合。

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